High-resolution data acquisition technique in broadband seismic observation systems

The dynamic range of the currently most widely used 24-bit seismic data acquisition devices is 10–20 d B lower than that of broadband seismometers, and this can affect the completeness of seismic waveform recordings under certain conditions. However, this problem is not easy to solve because of the lack of analog to digital converter(ADC) chips with more than 24 bits in the market. In this paper, we propose a method in which an adder, an integrator, a digital to analog converter chip, a field-programmable gate array, and an existing low-resolution ADC chip are used to build a third-order 16-bit oversampling delta-sigma modulator. This modulator is equipped with a digital decimation filter, thus facilitating higher resolution and larger dynamic range seismic data acquisition. Experimental results show that, within the 0.1–40 Hz frequency range, the circuit board's dynamic range reaches 158.2 d B, its resolution reaches 25.99 bits, and its linearity error is below 2.5 ppm, which is better than what is achieved by the commercial 24-bit ADC chips ADS1281 and CS5371. This demonstrates that the proposed method may alleviate or even completely resolve the amplitude-limitation problem that so commonly occurs with broadband observation instruments during strong earthquakes.

Waveform timing performance of a 5 GS/s fast pulse sampling module with DRS4

We first clarify timing issues of non-uniform sampling intervals regarding a 5 GS/s fast pulse sampling module with DRS4. A calibration strategy is proposed, and as a result, the waveform timing performance is improved to below 10 ps RMS. We then further evaluate waveform-timing performance of the module by comparing with a 10 GS/s oscilloscope in a setup with plastic scintillators and fast PMTs. Different waveform timing algorithms are employed for analysis, and the module shows comparable timing performance with that of the oscilloscope.