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A 10-bit column-parallel cyclic ADC for high-speed CMOS image sensors 被引量:2
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作者 韩烨 李全良 +1 位作者 石匆 吴南健 《Journal of Semiconductors》 EI CAS CSCD 2013年第8期177-182,共6页
This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS ci... This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors. 展开更多
关键词 CMOS image sensor column-parallel cyclic adc correlated double sampling offset cancellation
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A 430 mW 16 b 170 MS/s CMOS pipelined ADC with 77.2 dB SNR and 97.6 dB SFDR
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作者 张辉 李丹 +6 位作者 万磊 张辉 王海军 高远 朱腓利 王紫琪 丁学欣 《Journal of Semiconductors》 EI CAS CSCD 2016年第3期88-94,共7页
A 16-bit 170 MS/s pipelined ADC implemented in 0.18 m CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarg... A 16-bit 170 MS/s pipelined ADC implemented in 0.18 m CMOS process is presented in this paper. An improved digital calibration method and a linearized sampling front-end are employed to achieve a high SFDR. The enlarged full scale range makes it possible to obtain a high SNR with smaller sampling capacitors, thus achieving higher speed and low power. This ADC attains an SNR of 77.2 d BFS, an SFDR of 97.6 d Bc for a 10 MHz input signal, while preserving an SFDR 〉 80 d Bc up to 300 MHz input frequency. The ADC consumes 430 mW from a1.8 V supply and occupies a 17 mm^2 active area. 展开更多
关键词 pipelined adc calibration SHA-less IF sampling
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A precision sampling system for fast corrector power supply of photon source
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作者 Peng Liu F.L.Long Y.Z.Du 《Radiation Detection Technology and Methods》 CSCD 2023年第1期139-148,共10页
Purpose At present,the high-energy photon source(HEPS)is under construction in Beijing.HEPS has beam emittance lower than 40 pm rad.In order to ensure low beam emittance,a high-performance fast orbit feedback system(F... Purpose At present,the high-energy photon source(HEPS)is under construction in Beijing.HEPS has beam emittance lower than 40 pm rad.In order to ensure low beam emittance,a high-performance fast orbit feedback system(FOFB)is designed for fast and accurate correction of beam orbit.The FOFB needs to have the smallest adjustment step.Therefore,as the execution unit of the FOFB system,the output current resolution of the fast corrector power supply needs to be as small as possible.In FOFB systems,precise correction of beam orbit is required for fast corrector power supply with output current resolution better than 60μA.A precision digital sampling system needs to be designed to meet the high requirements of output current resolution.Method The precision operational amplifier is used to complete the scaling and sampling of signals.The precision operational amplifier is used as the front-end processing in the circuit design to complete the amplitude processing and filtering.Meanwhile,the precision operational amplifier is used as the driver of the precision analog to digital converter(ADC)chip.A precision ADC chips based on oversampling technology is used.With this scheme,the selected ADC chip can have the advantages of both high speed and high precision.A simulation prototype is built for test,and the performance parameters of key chips in the design are given.Results A precision voltage reference is used to test the designed digital sampling system.The test results showed that the acquisition system has an effective resolution of 21.6 bits.The HEPS fast corrector power supply is used for testing the developed precision sampling system.The test result showed that the output current resolution of fast corrector power supply is lower than 16μA. 展开更多
关键词 Photon source FOFB Fast corrector High precision Over sampling adc High resolution
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