An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasit...An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.展开更多
针对无线通信的能量效率和需求响应误差成本严重影响系统的运行成本,提出一种基于超密集组网结构的无线通信网络,在提升智能电网需求响应管理效率的同时,减少系统的运行成本。首先采用大规模天线的中心基站,保证智能电网需求响应的通信...针对无线通信的能量效率和需求响应误差成本严重影响系统的运行成本,提出一种基于超密集组网结构的无线通信网络,在提升智能电网需求响应管理效率的同时,减少系统的运行成本。首先采用大规模天线的中心基站,保证智能电网需求响应的通信稳定性,然后通过低精度模数转换/数模转换(analog to digital conversions/digital to analog conversions,ADCs/DACs)提高通信系统的能量效率,同时中心基站采用全双工工作模式,进一步降低通信时延。仿真结果表明,在保障需求响应误差成本的前提下,低精度ADCs/DACs可以有效地提升通信网络的能量效率,以降低通信网络的运行成本。展开更多
A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopt...A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.展开更多
基金Supported by National Science and Technology Major Project of China(No.2012ZX03004008)
文摘An error correction technique to achieve a 14-bit successive approximation register analog-to-digital converter(SAR ADC) is proposed. A tunable split capacitor is designed to eliminate the mismatches caused by parasitic capacitors. The linearity error of capacitor array caused by process mismatch is calibrated by a novel calibration capacitor array that can improve the sampling rate. The dual-comparator topology ensures both the speed and precision of the ADC. The simulation results show that the SAR ADC after calibration achieves 83.07 dB SNDR and 13.5 bit ENOB at 500 kilosamples/s.
文摘针对无线通信的能量效率和需求响应误差成本严重影响系统的运行成本,提出一种基于超密集组网结构的无线通信网络,在提升智能电网需求响应管理效率的同时,减少系统的运行成本。首先采用大规模天线的中心基站,保证智能电网需求响应的通信稳定性,然后通过低精度模数转换/数模转换(analog to digital conversions/digital to analog conversions,ADCs/DACs)提高通信系统的能量效率,同时中心基站采用全双工工作模式,进一步降低通信时延。仿真结果表明,在保障需求响应误差成本的前提下,低精度ADCs/DACs可以有效地提升通信网络的能量效率,以降低通信网络的运行成本。
基金supported by the National High Technology Research and Development Program of China(No.2006AA04A109)
文摘A high linearity,undersampling 14-bit 357 kSps cyclic analog-to-digital convert（ADC） is designed for a radio frequency identification transceiver system.The passive capacitor error-average（PCEA） technique is adopted for high accuracy.An improved PCEA sampling network,capable of eliminating the crosstalk path of two pipelined stages,is employed.Opamp sharing and the removal of the front-end sample and hold amplifier are utilized for low power dissipation and small chip area.An additional digital calibration block is added to compensate for the error due to defective layout design.The presented ADC is fabricated in a 180 nm CMOS process,occupying 0.65×1.6 mm^2. The input of the undersampling ADC achieves 15.5 MHz with more than 90 dB spurious free dynamic range（SFDR）, and the peak SFDR is as high as 106.4 dB with 2.431 MHz input.
