对红外探测器不断增长和提高的需求催生了第三代红外焦平面探测器技术。根据第三代红外探测器的概念,像素达到百万级,热灵敏度NETD达到1 m K量级是第三代制冷型高性能红外焦平面探测器的基本特征。计算结果表明读出电路需要达到1000 Me...对红外探测器不断增长和提高的需求催生了第三代红外焦平面探测器技术。根据第三代红外探测器的概念,像素达到百万级,热灵敏度NETD达到1 m K量级是第三代制冷型高性能红外焦平面探测器的基本特征。计算结果表明读出电路需要达到1000 Me-以上的电荷处理能力和100 d B左右的动态范围(Dynamic Range)才能满足上述第三代红外焦平面探测器需求。提出在像素内进行数字积分技术,以期突破传统模拟读出电路的电荷存储量和动态范围瓶颈限制,使高空间分辨率、高温度分辨率及高帧频的第三代高性能制冷型红外焦平面探测器得到实现。展开更多
近年来,卷积神经网络(Convolutional Neural Networks,CNN)在多个领域取得了快速的发展。然而受到传统冯·诺依曼结构中数据的存储模块与运算模块分离的影响,一定程度上限制了CNN性能的提升。本文介绍了一种以12T SRAM(Static Rando...近年来,卷积神经网络(Convolutional Neural Networks,CNN)在多个领域取得了快速的发展。然而受到传统冯·诺依曼结构中数据的存储模块与运算模块分离的影响,一定程度上限制了CNN性能的提升。本文介绍了一种以12T SRAM(Static Random-Access Memory,SRAM)单元为基础的存内计算结构。用于实现CNN中4bit输入与4bit权重的卷积运算。在CMOS工艺下对设计的电路进行仿真,在2GHz频率下实现了46.1~117.3TOPS/W(Tera Operation Per Second Per Watt,TOPS/W)的能效。展开更多
A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase...A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.展开更多
文摘对红外探测器不断增长和提高的需求催生了第三代红外焦平面探测器技术。根据第三代红外探测器的概念,像素达到百万级,热灵敏度NETD达到1 m K量级是第三代制冷型高性能红外焦平面探测器的基本特征。计算结果表明读出电路需要达到1000 Me-以上的电荷处理能力和100 d B左右的动态范围(Dynamic Range)才能满足上述第三代红外焦平面探测器需求。提出在像素内进行数字积分技术,以期突破传统模拟读出电路的电荷存储量和动态范围瓶颈限制,使高空间分辨率、高温度分辨率及高帧频的第三代高性能制冷型红外焦平面探测器得到实现。
文摘近年来,卷积神经网络(Convolutional Neural Networks,CNN)在多个领域取得了快速的发展。然而受到传统冯·诺依曼结构中数据的存储模块与运算模块分离的影响,一定程度上限制了CNN性能的提升。本文介绍了一种以12T SRAM(Static Random-Access Memory,SRAM)单元为基础的存内计算结构。用于实现CNN中4bit输入与4bit权重的卷积运算。在CMOS工艺下对设计的电路进行仿真,在2GHz频率下实现了46.1~117.3TOPS/W(Tera Operation Per Second Per Watt,TOPS/W)的能效。
基金Supported by National Natural Science Foundation of China (No.60806010,No.60976030)
文摘A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.
