CMOS Automatic Gain Control Circuit with DC Offset Cancellation for FM/cw Ladar

This paper presented an automatic gain control （AGC） circuit suitable for FM/cw ladar. The proposed architecture was based on two-stage variable gain amplifier （VGA） chain with a novel DC offset canceller circuit, which contained an improved Gilbert cell and a Gm-C feedback loop. To keep the VGA with a linearity in dB characteristic, an improved exponential gain control circuit was introduced. The AGC was implemented in 0.18 gm standard CMOS process. Simulation and measurement results verified that its gain ranged from -20 dB to 30 dB, and band- width ranged from 100 kHz to 10 MHz. Its power consumption was 19.8 mW under a voltage supply of 3.3 V.

Design and implementation of digital closed-loop drive control system of a MEMS gyroscope

In order to effectively control the working state of the gyroscope in drive mode, the drive characteristics of the micro electromechanical system （MEMS） gyroscope are analyzed in principle. A novel drive circuit for the MEMS gyroscope in digital closed-loop control is proposed, which utilizes a digital phase-locked loop （PLL） in frequency control and an automatic gain control （AGC） method in amplitude control. A digital processing circuit with a field programmable gate array （FPGA） is designed and the experiments are carried out. The results indicate that when the temperature changes, the drive frequency can automatically track the resonant frequency of gyroscope in drive mode and that of the oscillating amplitude holds at a set value. And at room temperature, the relative deviation of the drive frequency is 0.624 ×10^-6 and the oscillating amplitude is 8.0 ×10^-6, which are 0. 094% and 18. 39% of the analog control program, respectively. Therefore, the control solution of the digital PLL in frequency and the AGC in amplitude is feasible.

Response characteristics of sonar receiver under intense sound pulse

For anti-jamming and anti-countermeasure techniques of the sonar receiver, the response characteristics of the automatic gain control （AGC） circuit and the survivability of the prime circuit under strong interference are analyzed by simulations and experiments. An AGC simulation model based on the voltage control amplifier VCA810 prototype is proposed. Then static and dynamic simulations are realized with single frequency signal and linear frequency modulated （LFM） signal commonly used in the active sonar. Based on intense sound pulse （ISP） interference experiments, the real-time response characteristics of each module of the receiver are studied to verify the correctness of the model as well as the simulation results. Simulation and experiment results show that, under 252 dB/20 μs ISP interference, the specific sonar receiver will produce sustained cut top oscillation above 30 ms, which may affect the receiver and block the regular sonar signal.

Design of a 6.25 Gbps backplane SerDes with adaptive decision feedback equalization

A 6.25 Gbps SerDes core used in the high signed based on the OIF-CEI-02.0 standard. To speed backplane communication receiver has been decounteract the serious Inter-Syrmbol-Interference （ISI）, the core employed a half-rate four-tap decision feedback equalizer （DFE）. The equalizer used the Signsign least mean-squared （SS-LMS） algorithm to realize the coefficient adaptation. An automatic gain control （AGC） amplifier with the sign least mean-squared （S-LMS） algorithm has been used to compensate the transmission media loss. To recover the clock signal from the input data serial and provide for the DFE and AGC, a bang-bang clock recovery （BB-CR） is adopted. A third order phase loop loek （PLL） model was proposed to predict characteristics of the BB-CR. The core has been verified by behavioral modeling in MATLAB. The results indicate that the core can meet the specifications of the backplane receiver. The DFE recovered data over a 34＂ FR-4 backplane has a peak-to-peak jitter of 17 ps, a horizontal eye opening of 0.87 UI, and a vertical eye opening of 500 mVpp.

Linear-in-dB Variable-Gain Downconversion Mixer for Zero Intermediate Frequency Receivers

In-phase/quadrature （I/Q） mismatch is a key problem in zero intermediate frequency （ZIF） receiver architectures. Although integration and careful layout can alleviate I/Q mismatch, circuit and system level calibrations are also needed due to process variations and variable operating conditions. The amplitude im- balance between I/Q channels was calibrated using a modified R-2R ladder to achieve fine linear-in-dB variable gain. A downconversion mixer working in the 2,4-GHz band was developed for a wireless local area network （WLAN） ZIF receiver using 0.25μm complementary metal-oxide semiconductor （CMOS）. The twostage mixer configuration relaxes the tradeoff between noise and linearity. Experimental results verify the fine linear-in-dB variable conversion gain of the mixer, which can also be used as part of an automatic gain control （AGC）loop.