A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) ...A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91 6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.展开更多
The paper puts forward a method on controlling the AM-OLED panel to display image with high gray scale levels. It also gives an ASIC design sample to implement this method. A twenty sub-fields scan scheme has been tak...The paper puts forward a method on controlling the AM-OLED panel to display image with high gray scale levels. It also gives an ASIC design sample to implement this method. A twenty sub-fields scan scheme has been taken into use in the chip to display 256 gray scale levels on a QVGA resolution AM-OLED display screen. The functions of image scaling and rotating have also been implemented for multiply application. The simulation and chip test result show that the chip design has met the design requirements.展开更多
文摘A novel ASIC design of changeable-point digital pulse compression (DPC) chip is presented. System hardware resource is reduced to one third of the traditional design method through operations sharing hardware, (i.e.) let FFT, complex multiplication and IFFT be fulfilled with the same hardware structure. Block-floating-point scaling is used to enhance the dynamic range and computation accuracy. This design applies parallel pipeline structure and the radix-4 butterfly operation to improve the processing speed. In addition, a triple-memory-space(TMS) configuration is used that allows input, computation and output operations to be overlapped, so that the dual-butterfly unit is never left in an idle state waiting for I/O operation. The whole design is implemented with only one chip of XC2V500-5 FPGA. It can implement 1 024-point DPC within 91 6 μs.The output data is converted to floating-point formation to achieve seamless interface with TMS320C6701. The validity of the design is verified by simulation and measurement results.
基金Project supported by the Science and Technology Commission of Shanghai Municipality(Grant No.09530708600)the Shanghai AM Foundation(Grant No.09700714000)
文摘The paper puts forward a method on controlling the AM-OLED panel to display image with high gray scale levels. It also gives an ASIC design sample to implement this method. A twenty sub-fields scan scheme has been taken into use in the chip to display 256 gray scale levels on a QVGA resolution AM-OLED display screen. The functions of image scaling and rotating have also been implemented for multiply application. The simulation and chip test result show that the chip design has met the design requirements.
