Based on the analysis of the existing hard IP core testing technology, the hard IP core nondestructive testing technology was studied, according to the verification requirements of a large number of hard IP core preci...Based on the analysis of the existing hard IP core testing technology, the hard IP core nondestructive testing technology was studied, according to the verification requirements of a large number of hard IP core precise and fast testing. Combined with the external automatic test equipment (ATE) and the on-chip evaluation circuit, a general evaluation system of simulating user system on chip (SOC) with signal timing calibration and compensation by software and hardware compensation structures were introduced to realize the function, performance and reliability verification of the hard IP core. The design and verification of a random access memory (SRAM) hard IP core based on an on-chip evaluation circuit was actually completed, and the key timing parameters of the hard IP core were tested. The address setup time parameter was taken as an example to analyze the specific testing method and the test results were obtained. With this testing technology, the accuracy of testing the timing parameters of hard IP core can reach pS level, compared with the hard IP core packaged test, the accuracy of the result data is fully reflected.展开更多
文摘Based on the analysis of the existing hard IP core testing technology, the hard IP core nondestructive testing technology was studied, according to the verification requirements of a large number of hard IP core precise and fast testing. Combined with the external automatic test equipment (ATE) and the on-chip evaluation circuit, a general evaluation system of simulating user system on chip (SOC) with signal timing calibration and compensation by software and hardware compensation structures were introduced to realize the function, performance and reliability verification of the hard IP core. The design and verification of a random access memory (SRAM) hard IP core based on an on-chip evaluation circuit was actually completed, and the key timing parameters of the hard IP core were tested. The address setup time parameter was taken as an example to analyze the specific testing method and the test results were obtained. With this testing technology, the accuracy of testing the timing parameters of hard IP core can reach pS level, compared with the hard IP core packaged test, the accuracy of the result data is fully reflected.
