The paper presents a parallel ATPG algorithm - PTGBP, which aims at decreasing the complexity of the ATPG by partitioning circuit under test (CUT) to big function blocks (BFB) and processing them parallelly. PTGBP ado...The paper presents a parallel ATPG algorithm - PTGBP, which aims at decreasing the complexity of the ATPG by partitioning circuit under test (CUT) to big function blocks (BFB) and processing them parallelly. PTGBP adopts hybrid circuit mode and hybrid fault model, and organizes the parallel course in term of master/slave mode. Master processor loads the whole netlist of CUT based on BFB, every slave processor loads logic level (gate/function block/basic logic units) netlist of a BFB. Test generation (TG) uses BFB input/output s-a-0/s-a-1 fault model; fault simulation uses logic level single stuck fault model. Master controls the PTGBP’s running course and ensures the correctness of its running result; slaves provide the results of fault sensitization compatible computation and fault simulation to master parallelly. PTGBP algorithm is under implementation.展开更多
Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic t...Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.展开更多
This paper analyzes structural characteristics of signal vectors in combinational circuits with RTL description. Then, this paper presents the concept of the Basic Similar Circuit (BSC), a circuit constructed by compr...This paper analyzes structural characteristics of signal vectors in combinational circuits with RTL description. Then, this paper presents the concept of the Basic Similar Circuit (BSC), a circuit constructed by compressing the bit-width of vectored vectors in the original circuit. BSC shrinks the scale of the original circuit, thus improving the ATPG efficiency. Test patterns are derived from adjustment and assembling of precomputed sub-circuit test sets. Based on the deterministic algorithm, the ATPG method presented in this paper combines deterministic algorithms and undetermined methods.展开更多
The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms...The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.展开更多
The subunit Ⅱ of chloroplast ATP synthase is one of the two peripheral stalks, which associates the catalytic CF1 with mem-brane-spanning CFo . Although the structural and functional roles of chloroplast ATP synthase...The subunit Ⅱ of chloroplast ATP synthase is one of the two peripheral stalks, which associates the catalytic CF1 with mem-brane-spanning CFo . Although the structural and functional roles of chloroplast ATP synthase have been extensively examined, the physiological significance of subunit Ⅱ in vivo is still unclear. In this work, we identified one Arabidopsis T-DNA insertion mutant of atpG gene encoding the subunit Ⅱ of chloroplast ATP synthase. The atpg null mutant displayed an albino lethal pheno-type, as it could not grow photoautotrophically. Transmission electron microscopy analysis showed that chloroplasts of atpg lacked the organized thylakoid membranes. Loss of subunit Ⅱ affected the accumulation of CF1-CFo complex, however, it did not seem to have an effect on the CF1 assembly. The light induced ATP formation of atpg was significantly reduced compared with the wild type. Based on these results, we suggested that ATPG was essential for the accumulation and function of chloroplast ATP synthase.展开更多
基金Supported by National Natural Science Founding of China.
文摘The paper presents a parallel ATPG algorithm - PTGBP, which aims at decreasing the complexity of the ATPG by partitioning circuit under test (CUT) to big function blocks (BFB) and processing them parallelly. PTGBP adopts hybrid circuit mode and hybrid fault model, and organizes the parallel course in term of master/slave mode. Master processor loads the whole netlist of CUT based on BFB, every slave processor loads logic level (gate/function block/basic logic units) netlist of a BFB. Test generation (TG) uses BFB input/output s-a-0/s-a-1 fault model; fault simulation uses logic level single stuck fault model. Master controls the PTGBP’s running course and ensures the correctness of its running result; slaves provide the results of fault sensitization compatible computation and fault simulation to master parallelly. PTGBP algorithm is under implementation.
文摘Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.
基金supported by National Natural Science Foundation of China under grant No.69733010,69973016
文摘This paper analyzes structural characteristics of signal vectors in combinational circuits with RTL description. Then, this paper presents the concept of the Basic Similar Circuit (BSC), a circuit constructed by compressing the bit-width of vectored vectors in the original circuit. BSC shrinks the scale of the original circuit, thus improving the ATPG efficiency. Test patterns are derived from adjustment and assembling of precomputed sub-circuit test sets. Based on the deterministic algorithm, the ATPG method presented in this paper combines deterministic algorithms and undetermined methods.
基金supported by National Natural Science Foundation of China under grant No.69733010.
文摘The paper proposes an ATPG method for the Synchronous Sequential circuits described in synthesizable VHDL behavioral RTL. The method extracts a controlling tree for each process in the behavioral description and forms a graph to represent the static data-flow for the target circuit. A fault-model is defined at RT-Level. The ATPG method is then presented. Experimental results show that the ATPG method is time effective and can generate tests with fairly good quality, the fault coverage of some circuits is to be enhanced though.
基金supported by the National Natural Science Foundation of China (31070215 and 31100181)the State Key Basic Research and Development Program of China (2009CB118504)
文摘The subunit Ⅱ of chloroplast ATP synthase is one of the two peripheral stalks, which associates the catalytic CF1 with mem-brane-spanning CFo . Although the structural and functional roles of chloroplast ATP synthase have been extensively examined, the physiological significance of subunit Ⅱ in vivo is still unclear. In this work, we identified one Arabidopsis T-DNA insertion mutant of atpG gene encoding the subunit Ⅱ of chloroplast ATP synthase. The atpg null mutant displayed an albino lethal pheno-type, as it could not grow photoautotrophically. Transmission electron microscopy analysis showed that chloroplasts of atpg lacked the organized thylakoid membranes. Loss of subunit Ⅱ affected the accumulation of CF1-CFo complex, however, it did not seem to have an effect on the CF1 assembly. The light induced ATP formation of atpg was significantly reduced compared with the wild type. Based on these results, we suggested that ATPG was essential for the accumulation and function of chloroplast ATP synthase.
