With the rapid advancement of wearable devices,Human Activities Recognition(HAR)based on these devices has emerged as a prominent research field.The objective of this study is to enhance the recognition performance of...With the rapid advancement of wearable devices,Human Activities Recognition(HAR)based on these devices has emerged as a prominent research field.The objective of this study is to enhance the recognition performance of HAR by proposing an LSTM-1DCNN recognition algorithm that utilizes a single triaxial accelerometer.This algorithm comprises two branches:one branch consists of a Long and Short-Term Memory Network(LSTM),while the other parallel branch incorporates a one-dimensional Convolutional Neural Network(1DCNN).The parallel architecture of LSTM-1DCNN initially extracts spatial and temporal features from the accelerometer data separately,which are then concatenated and fed into a fully connected neural network for information fusion.In the LSTM-1DCNN architecture,the 1DCNN branch primarily focuses on extracting spatial features during convolution operations,whereas the LSTM branch mainly captures temporal features.Nine sets of accelerometer data from five publicly available HAR datasets are employed for training and evaluation purposes.The performance of the proposed LSTM-1DCNN model is compared with five other HAR algorithms including Decision Tree,Random Forest,Support Vector Machine,1DCNN,and LSTM on these five public datasets.Experimental results demonstrate that the F1-score achieved by the proposed LSTM-1DCNN ranges from 90.36%to 99.68%,with a mean value of 96.22%and standard deviation of 0.03 across all evaluated metrics on these five public datasets-outperforming other existing HAR algorithms significantly in terms of evaluation metrics used in this study.Finally the proposed LSTM-1DCNN is validated in real-world applications by collecting acceleration data of seven human activities for training and testing purposes.Subsequently,the trained HAR algorithm is deployed on Android phones to evaluate its performance.Experimental results demonstrate that the proposed LSTM-1DCNN algorithm achieves an impressive F1-score of 97.67%on our self-built dataset.In conclusion,the fusion of temporal and spatial information in the measured data contributes to the excellent HAR performance and robustness exhibited by the proposed 1DCNN-LSTM architecture.展开更多
In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack t...In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.展开更多
基金supported by the Guangxi University of Science and Technology,Liuzhou,China,sponsored by the Researchers Supporting Project(No.XiaoKeBo21Z27,The Construction of Electronic Information Team supported by Artificial Intelligence Theory and Three-dimensional Visual Technology,Yuesheng Zhao)supported by the 2022 Laboratory Fund Project of the Key Laboratory of Space-Based Integrated Information System(No.SpaceInfoNet20221120,Research on the Key Technologies of Intelligent Spatiotemporal Data Engine Based on Space-Based Information Network,Yuesheng Zhao)supported by the 2023 Guangxi University Young and Middle-Aged Teachers’Basic Scientific Research Ability Improvement Project(No.2023KY0352,Research on the Recognition of Psychological Abnormalities in College Students Based on the Fusion of Pulse and EEG Techniques,Yutong Luo).
文摘With the rapid advancement of wearable devices,Human Activities Recognition(HAR)based on these devices has emerged as a prominent research field.The objective of this study is to enhance the recognition performance of HAR by proposing an LSTM-1DCNN recognition algorithm that utilizes a single triaxial accelerometer.This algorithm comprises two branches:one branch consists of a Long and Short-Term Memory Network(LSTM),while the other parallel branch incorporates a one-dimensional Convolutional Neural Network(1DCNN).The parallel architecture of LSTM-1DCNN initially extracts spatial and temporal features from the accelerometer data separately,which are then concatenated and fed into a fully connected neural network for information fusion.In the LSTM-1DCNN architecture,the 1DCNN branch primarily focuses on extracting spatial features during convolution operations,whereas the LSTM branch mainly captures temporal features.Nine sets of accelerometer data from five publicly available HAR datasets are employed for training and evaluation purposes.The performance of the proposed LSTM-1DCNN model is compared with five other HAR algorithms including Decision Tree,Random Forest,Support Vector Machine,1DCNN,and LSTM on these five public datasets.Experimental results demonstrate that the F1-score achieved by the proposed LSTM-1DCNN ranges from 90.36%to 99.68%,with a mean value of 96.22%and standard deviation of 0.03 across all evaluated metrics on these five public datasets-outperforming other existing HAR algorithms significantly in terms of evaluation metrics used in this study.Finally the proposed LSTM-1DCNN is validated in real-world applications by collecting acceleration data of seven human activities for training and testing purposes.Subsequently,the trained HAR algorithm is deployed on Android phones to evaluate its performance.Experimental results demonstrate that the proposed LSTM-1DCNN algorithm achieves an impressive F1-score of 97.67%on our self-built dataset.In conclusion,the fusion of temporal and spatial information in the measured data contributes to the excellent HAR performance and robustness exhibited by the proposed 1DCNN-LSTM architecture.
文摘In this paper, four new hybrid digital circuit design techniques, namely, hybrid multi-threshold CMOS complete stack technique, hybrid multi-threshold CMOS partial stack technique, hybrid super cutoff complete stack technique and hybrid super cutoff partial stack technique, have been proposed to reduce the subthreshold leakage power dissipation in standby modes. Techniques available in literature are compared with our proposed hybrid circuit design techniques. Performance parameters such as subthreshold leakage power dissipation in active and standby modes, dynamic power dissipation and propagation delay, are compared using existing and proposed hybrid techniques for a two input AND gate. Reduction of subthreshold leakage power dissipation in standby mode is given more importance, in comparison with the other circuit design performance parameters. It is found that there is reduction in subthreshold leakage power dissipation in standby and active modes by 3.5× and 1.15× respectively using the proposed hybrid super cutoff complete stack technique as compared to the existing multi-threshold CMOS (MTCMOS) technique. Also a saving of 2.50× and 1.04× in subthreshold leakage power dissipation in standby and active modes respectively were observed using hybrid super cutoff complete stack technique as compared to the existing super cutoff CMOS (SCCMOS) technique. The proposed hybrid super cutoff stack technique proved to perform better in terms of subthreshold leakage power dissipation in standby mode in comparison with other techniques. Simulation results using Microwind EDA tool in 65 nm CMOS technology is provided in this paper.
