Currently,the growth of micro and nano(very large scale integration-ultra large-scale integration)electronics technology has greatly impacted biomedical signal processing devices.These high-speed micro and nano techno...Currently,the growth of micro and nano(very large scale integration-ultra large-scale integration)electronics technology has greatly impacted biomedical signal processing devices.These high-speed micro and nano technology devices are very reliable despite their capacity to operate at tremendous speed,and can be designed to consume less power in minimum response time,which is particularly useful in biomedical products.The rapid technological scaling of the metal-oxide-semi-conductor(MOS)devices aids in mapping multiple applications for a specific purpose on a single chip which motivates us to design a sophisticated,small and reliable application specific integrated circuit(ASIC)chip for future real time medical signal separation and processing(digital stetho-scopes and digital microelectromechanical systems(MEMS)microphone).In this paper,ASIC level implementation of the adaptive line enhancer design using adaptive filtering algorithms(least mean square(LMS)and normalized least mean square(NLMS))integrated design is used to separate the real-time auscultation sound signals effectively.Adaptive line enhancer(ALE)design is imple-mented in Verilog hardware description language(HDL)language to obtain both the network and adaptive algorithm in cadence Taiwan Semiconductor Manufacturing Company(TSMC)90 nm standard cell library environment for ASIC level implementation.Native compiled simulator(NC)sim and RC lab were used for functional verification and design constraints and the physical design is implemented in Encounter to obtain the Geometric Data Stream(GDS II).In this architecture,the area occupied is 0.08 mm,the total power consumed is 5.05 mW and the computation time of the proposed system is 0.82μs for LMS design and the area occupied is 0.14 mm,the total power consumed is 4.54 mW and the computation time of the proposed system is 0.03μs for NLMS design that will pave a better way in future electronic stethoscope design.展开更多
It is well known that the adaptive line enhancer (ALE) is effective detector of CW signal with unknown frequency in the background of white noise. The system processing gain of ALE, when the LMS algorithm is used, how...It is well known that the adaptive line enhancer (ALE) is effective detector of CW signal with unknown frequency in the background of white noise. The system processing gain of ALE, when the LMS algorithm is used, however, is not satisfactory because of the presence of iterative noise and weight noise. In this paper, the coherent accumulation algorithm of ALE, called as ALECA, is suggested. It is shown that the adaptive filter employing this new algorithm possesses the ARMA structure. The experimental results also show that the processing gain of ALECA is about 14dB higher than that of conventional ALE.展开更多
文摘Currently,the growth of micro and nano(very large scale integration-ultra large-scale integration)electronics technology has greatly impacted biomedical signal processing devices.These high-speed micro and nano technology devices are very reliable despite their capacity to operate at tremendous speed,and can be designed to consume less power in minimum response time,which is particularly useful in biomedical products.The rapid technological scaling of the metal-oxide-semi-conductor(MOS)devices aids in mapping multiple applications for a specific purpose on a single chip which motivates us to design a sophisticated,small and reliable application specific integrated circuit(ASIC)chip for future real time medical signal separation and processing(digital stetho-scopes and digital microelectromechanical systems(MEMS)microphone).In this paper,ASIC level implementation of the adaptive line enhancer design using adaptive filtering algorithms(least mean square(LMS)and normalized least mean square(NLMS))integrated design is used to separate the real-time auscultation sound signals effectively.Adaptive line enhancer(ALE)design is imple-mented in Verilog hardware description language(HDL)language to obtain both the network and adaptive algorithm in cadence Taiwan Semiconductor Manufacturing Company(TSMC)90 nm standard cell library environment for ASIC level implementation.Native compiled simulator(NC)sim and RC lab were used for functional verification and design constraints and the physical design is implemented in Encounter to obtain the Geometric Data Stream(GDS II).In this architecture,the area occupied is 0.08 mm,the total power consumed is 5.05 mW and the computation time of the proposed system is 0.82μs for LMS design and the area occupied is 0.14 mm,the total power consumed is 4.54 mW and the computation time of the proposed system is 0.03μs for NLMS design that will pave a better way in future electronic stethoscope design.
文摘It is well known that the adaptive line enhancer (ALE) is effective detector of CW signal with unknown frequency in the background of white noise. The system processing gain of ALE, when the LMS algorithm is used, however, is not satisfactory because of the presence of iterative noise and weight noise. In this paper, the coherent accumulation algorithm of ALE, called as ALECA, is suggested. It is shown that the adaptive filter employing this new algorithm possesses the ARMA structure. The experimental results also show that the processing gain of ALECA is about 14dB higher than that of conventional ALE.