Numerical Simulation of Azimuthal Uniformity of Injection Currents in Single-Point-Feed Induction Voltage Adders

In order to investigate the injection current uniformity around the induction cell bores, two fully electromagnetic （EM） models are respectively established for a single-stage induction cell and an induction voltage adder （IVA） with three cells stacked in series, without considering electron emission. By means of these two models, some factors affecting the injection current uni- formity are simulated and analyzed, such as the impedances of adders and loads, cell locations, and feed timing of parallel driving pulses. Simulation results indicate that higher impedances of adder and loads are slightly beneficial to improve injection current uniformity. As the impedances of adder and loads increase from 5 Ω to 30Ω, the asymmetric coefficient of feed currents decreases from 10.3% to 6.6%. The current non-uniformity within the first cell is a little worse than that in other downstream cells. Simulation results also show that the feed timing would greatly affect current waveforms, and consequently cause some distortion in pulse fronts of cell output voltages. For a given driving pulse with duration time of 70-80 ns, the feed timing with a time deviation of less than 20 ns is acceptable for the three-cell IVAs, just causing the rise time of output voltages to increase about 5 ns at most and making the peak voltage decrease by 3.5%.

Fast Signed-Digit Multi-operand Decimal Adders

Decimal arithmetic is desirable for high precision requirements of many financial, industrial and scientific applications. Furthermore, hardware support for decimal arithmetic has gained momentum with IEEE 754-2008, which standardized decimal floating-point. This paper presents a new architecture for two operand and multi-operand signed-digit decimal addition. Signed-digit architectures are advantageous because there are no carry-propagate chains. The proposed signed-digit adder reduces the critical path delay by parallelizing the correction stage inherent to decimal addition. For performance evaluation, we synthesize and compare multiple unsigned and signed-digit multi-operand decimal adder architectures on 0.18μm CMOS VLSI technology. Synthesis results for 2, 4, 8, and 16 operands with 8 decimal digits provide critical data in determining each adder's performance and scalability.

Introducing scalable 1-bit full adders for designing quantum-dot cellular automata arithmetic circuits

Designing logic circuits using complementary metal-oxide-semiconductor(CMOS)technology at the nano scale has been faced with various challenges recently.Undesirable leakage currents,the short-effect channel,and high energy dissipation are some of the concerns.Quantum-dot cellular automata(QCA)represent an appropriate alternative for possible CMOS replacement in the future because it consumes an insignificant amount of energy compared to the standard CMOS.The key point of designing arithmetic circuits is based on the structure of a 1-bit full adder.A low-complexity full adder block is beneficial for developing various intricate structures.This paper represents scalable 1-bit QCA full adder structures based on cell interaction.Our proposed full adders encompass preference aspects of QCA design,such as a low number of cells used,low latency,and small area occupation.Also,the proposed structures have been expanded to larger circuits,including a 4-bit ripple carry adder(RCA),a 4-bit ripple borrow subtractor(RBS),an add/sub circuit,and a 2-bit array multiplier.All designs were simulated and verified using QCA Designer-E version 2.2.This tool can estimate the energy dissipation as well as evaluate the performance of the circuits.Simulation results showed that the proposed designs are efficient in complexity,area,latency,cost,and energy dissipation.

Performance Measurement of Energy Efficient and Highly Scalable Hybrid Adder

The adders are the vital arithmetic operation for any arithmetic operations like multiplication,subtraction,and division.Binary number additions are performed by the digital circuit known as the adder.In VLSI(Very Large Scale Integration),the full adder is a basic component as it plays a major role in designing the integrated circuits applications.To minimize the power,various adder designs are implemented and each implemented designs undergo defined drawbacks.The designed adder requires high power when the driving capability is perfect and requires low power when the delay occurred is more.To overcome such issues and to obtain better performance,a novel parallel adder is proposed.The design of adder is initiated with 1 bit and has been extended up to 32 bits so as verify its scalability.This proposed novel parallel adder is attained from the carry look-ahead adder.The merits of this suggested adder are better speed,power consumption and delay,and the capability in driving.Thus designed adders are verified for different supply,delay,power,leakage and its performance is found to be superior to competitive Manchester Carry Chain Adder(MCCA),Carry Look Ahead Adder(CLAA),Carry Select Adder(CSLA),Carry Select Adder(CSA)and other adders.

高性能全加器电路版图优化设计研究

在现有全加器研究基础上,提出一种高性能全加器改进电路(improved full adder circuit,IFAC),通过改进全加器电路结构,优化电路元件工作数量,旨在提升加法器逻辑功能与运行状态。采用Candence软件搭载130 nm芯片锻造工艺,引入欧拉路径快速判寻法设计其电路版图,验证版图规则的合理性,并利用版图验证工具Dracula对电路进行仿真测试,结果表明本文所设计的全加器较常规全加器在处理复杂网络精确度、传输延迟时间、低功耗稳定运行及芯片面积方面有所提升。

高速浮点乘法器设计

设计了一种符合IEEE-754标准的32bits高速CMOS浮点乘法器。该乘法器采用MBA算法和基于4:2compressor的树型结构完成CarrySave形式的部分积压缩,再由高速CarrySelect加法器求得乘积。电路设计采用了新型的高速加法运算单元。乘法器采用0.35μm制程,内含19,197个晶体管。3.3V工作电压下(室温),乘法器延迟时间为3.807ns,功耗为107mW@100MHz。

尿纤维连接蛋白检测在膀胱癌患者中的临床应用

目的:探讨尿纤维连接蛋白(Fibronectin,Fn)在膀胱癌患者中的临床应用价值。方法:采用ELISA检测73例膀胱癌患者(组1)、45例其他泌尿生殖系统疾病患者(组2)和50例健康人的尿Fn含量(对照组,组3),并同时测定其尿肌酐(Creatin,Cr),计算尿Fn/尿Cr比值。比较各组人群尿Fn、尿Fn/Cr之间的差异,并分析不同肿瘤分期分级膀胱癌患者的尿Fn、尿Fn/Cr比值之间的差异。结果:膀胱癌患者组尿Fn含量(618·51±368·54)μg/L、Fn/Cr比值(166·03±298·65)mg/mol明显高于对照组的尿Fn含量(175·17±91·89)μg/L、尿Fn/Cr比值(31·37±34·04)mg/mol(P=0·0063,P=0·026)及其他泌尿生殖系统疾病患者组的尿Fn含量(214·48±142·40)μg/L、尿Fn/Cr比值(40·19±73·71)mg/mol(P=0·0089,P=0·047)。受试者工作曲线(ReceiverOperatingCharacteristicCurve,ROC曲线)显示:尿Fn诊断膀胱癌的灵敏度和特异度分别为78·1%和76·2%,尿Fn/Cr诊断膀胱癌的灵敏度和特异度为83·1%和79·2%。另外,不同肿瘤分期分级的膀胱癌患者的尿Fn含量,尿Fn/Cr比值也有明显差异。结论:尿Fn和Fn/Cr在膀胱癌患者的临床诊断方面有着重要的应用价值,是诊断膀胱癌的一种较理想的实验室指标,并可用于膀胱癌患者的预后评估。

基于修正ANT逻辑高速树形32 BitCarry Lookahead加法器

一种用修正全NMOS管逻辑(ANT)实现的树形结构高速32bitcarryLookahead加法器,使用两相时钟动态CMOS逻辑、修正不反向ANT逻辑和二进制树形结构实现。该加法器运用0.25μm工艺,文中给出了修正ANT逻辑中所有晶体管的宽长尺寸和仿真结果,最高工作频率为2GHz,计算结果在3.5个时钟周期后有效。

Efficient CNTFET-based Ternary Full Adder Cells for Nanoelectronics

This paper presents two new efficient ternary Full Adder cells for nanoelectronics. These CNTFETbased ternary Full Adders are designed based on the unique characteristics of the CNTFET device, such as the capability of setting the desired threshold voltages by adopting proper diameters for the nanotubes as well as the same carrier mobilities for the N-type and P-type devices. These characteristics of CNTFETs make them very suitable for designing high-performance multiple-Vth structures. The proposed structures reduce the number of the transistors considerably and have very high driving capability. The presented ternary Full Adders are simulated using Synopsys HSPICE with 32 nm CNTFET technology to evaluate their performance and to confirm their correct operation.

Design of Multi-Valued Logic Circuit Using Carbon Nano Tube Field Transistors

The design of a three-input logic circuit using carbon nanotube field effect transistors(CNTFETs)is presented.Ternary logic must be an exact replacement for dual logic since it performs straightforwardly in digital devices,which is why this design is so popular,and it also reduces chip area,both of which are examples of circuit overheads.The proposed module we have investigated is a triple-logic-based one,based on advanced technology CNTFETs and an emphasis on minimizing delay times at various values,as well as comparisons of the design working with various load capacitances.Comparing the proposed design with the existing design,the delay times was reduced from 66.32 to 16.41 ps,i.e.,a 75.26%reduction.However,the power dissipation was not optimized,and increased by 1.44%compared to the existing adder.The number of transistors was also reduced,and the product of power and delay(P∗D)achieved a value of 0.0498053 fJ.An improvement at 1 V was also achieved.A load capacitance(fF)was measured at different values,and the average delay measured for different values of capacitance had a maximum of 83.60 ps and a minimum of 22.54 ps,with a range of 61.06 ps.The power dissipations ranged from a minimum of 3.38μW to a maximum of 6.49μW.Based on these results,the use of this CNTFET half-adder design in multiple Boolean circuits will be a useful addition to circuit design.

Research of magnetic self-balance used in a repetitive high voltage rectangular waveform pulse adder

Compared with a sinusoidal operation, pulsed operation has more homogeneity and more efficiency in dielectric barrier discharge. In this paper, an improved pulse adder is designed and assembled to create repetitive high voltage rectangular pulses when resistive loads or capacitive loads exist. Beyond the normal pulse adder based on solid-state switches, additional metal- oxide-semiconductor field effect transistors are used in each stage for a faster falling edge. Further, the voltage difference between stages is eliminated by balancing windings. In this paper, we represent our theoretical derivation, software simulations and hardware experiments on magnetic self-balance. The experiments show that the voltage difference between stages is eliminated by balancing windings, which matches the result of simulations with almost identical circuits and parameters.

Measurement Uncertainty and Error Analysis

12001 Transformational Logic of Numbers of PurseEquivalence and its Error. Xiao Mingyao: 1(3). 1980pp 190--197Multiplier or counter --type adder can be usually used torealize the multiplication of two multidigit figures. Thispaper Introduces a Simple method, namely. the

A Novel Design of Octal-Valued Logic Full Adder Using Light Color State Model

Due to the demand of high computational speed for processing big data that requires complex data manipulations in a timely manner,the need for extending classical logic to construct new multi-valued optical models becomes a challenging and promising research area.This paper establishes a novel octal-valued logic design model with new optical gates construction based on the hypothesis of Light Color State Model to provide an efficient solution to the limitations of computational processing inherent in the electronics computing.We provide new mathematical definitions for both of the binary OR function and the PLUS operation in multi valued logic that is used as the basis of novel construction for the optical full adder model.Four case studies were used to assure the validity of the proposed adder.These cases proved that the proposed optical 8-valued logic models provide significantly more information to be packed within a single bit and therefore the abilities of data representation and processing is increased.

Quantum legitimacy of reversible gate and a new design of multiplier based on R gate

Quantum full adders play a key role in the design of quantum computers.The efficiency of a quantum adder directly determines the speed of the quantum computer,and its complexity is closely related to the difficulty and the cost of building a quantum computer.The existed full adder based on R gate is a great design but it is not suitable to construct a quantum multiplier.We show the quantum legitimacy of some common reversible gates,then use R gate to propose a new design of a quantum full adder.We utilize the new designed quantum full adder to optimize the quantum multiplier which is based on R gate.It is shown that the new designed one can be optimized by a local optimization rule so that it will have lower quantum cost than before.

Designing a Full Adder Circuit Based on Quasi-Floating Gate

Since in designing the full adder circuits, full adders have been generally taken into account, so as in this paper it has been attempted to represent a full adder cell with a significant efficiency of power, speed and leakage current levels. For this objective, a comparison between five full adder circuits has been provided. Applying floating gate technology and refresh circuits in the full adder cell lead to the reduction of leakage current on the gate node. The simulations were accomplished in this paper, through HSPICE software and 65 nm CMOS technology. The simulation results indicate the considerable efficiency of power consumption, speed and leakage current in the full adder cell rather than other cells.

OPTIMIZED REVERSIBLE ARITHMETIC LOGIC UNITS

Arithmetic Logic Unit(ALU) as one of the main parts of any computing hardware plays an important role in digital computers. In quantum computers which can be realized by reversible logics and circuits, reversible ALUs should be designed. In this paper, we proposed three different designs for reversible 1-bit ALUs using our proposed 3×3 and 4×4 reversible gates called MEB3 and MEB4(Moallem Ehsanpour Bolhasani) gates, respectively. The first proposed reversible ALU consists of six logical operations. The second proposed ALU consists of eight operations, two arithmetic, and six logical operations. And finally, the third proposed ALU consists of sixteen operations, four arithmetic operations, and twelve logical operations. Our proposed ALUs can be used to construct efficient quantum computers in nanotechnology, because the proposed designs are better than the existing designs in terms of quantum cost, constant input, reversible gates used, hardware complexity, and functions generated.

Defect and Temperature Effects on Complex Quantum-Dot Cellular Automata Devices

The authors present an analysis of the fault tolerant properties and the effects of temperature on an exclusive OR (XOR) gate and a full adder device implemented using quantum-dot cellular automata (QCA) structures. A Hubbard-type Hamiltonian and the Inter-cellular Hartree approximation have been used for modeling, and a uniform random distribution has been implemented for the simulated dot displacements within cells. We have shown characteristic features of all four possible input configurations for the XOR device. The device performance degrades significantly as the magnitude of defects and the temperature increase. Our results show that the fault-tolerant characteristics of an XOR device are highly dependent on the input configurations. The input signal that travels through the wire crossing (also called a crossover) in the central part of the device weakens the signal significantly. The presence of multiple wire crossings in the full adder design has a major impact on the functionality of the device. Even at absolute zero temperature, the effect of the dot displacement defect is very significant. We have observed that the breakdown characteristic is much more pronounced in the full adder than in any other devices under investigation.

A Low-Area, Low-Power Dynamically Reconfigurable 64-Bit Media Signal Processing Adder

Multimedia devices like cellphones, radios, televisions, and computers require low-area and energy-efficient dynamically reconfigurable data paths to process the greedy computation algorithms for real-time audio/video signal and image processing. In this paper, a novel low-area, energy-efficient 64-bit dynamically reconfigurable adder is presented. This adder can be run-time configured to different reconfigurable word lengths based on the partition signal commands provided. Moreover, the design is partitioned into sub-blocks based on functionality to save power, i.e., configuring the computation only for the necessary data path, thus avoiding the unnecessary switching power from the data path computed values that do not get used. Only functions that are needed are powered on, and the rest of the functionality is powered off. The proposed 64-bit dynamically reconfigurable media signal processing (MSP) adder is implemented in the 180 nm CMOS technology at 1.8 V, requiring an area of 39,478 μm2 and a power of 79.24 mW. The dynamic MSP adder achieves a 15.7% reduction in area and a 59.2% reduction in power than the 64-bit MSP adder.

Permutation Algebra for Constructing Reversible Circuits

In this paper, we show that the algebra of permutation group is one of the inherent structures of reversible logic for quantum computation. In this venture, we discuss necessary properties of cycle and transposition to reveal the potential of permutation algebra for reversible logic. Then we present an efficient method which naturally interconnects the structure of reversible logic with the expression of cycle and corresponding transpositions. Finally we discuss several examples which show that the algebra can be effectively used to construct complex gates as well.

Novel Adder Circuits Based On Quantum-Dot Cellular Automata (QCA)

Quantum-dot cellular automaton (QCA) is a novel nanotechnology that provides a very different computation platform than traditional CMOS, in which polarization of electrons indicates the digital information. This paper demonstrates designing combinational circuits based on quantum-dot cellular automata (QCA) nanotechnology, which offers a way to implement logic and all interconnections with only one homogeneous layer of cells. In this paper, the authors have proposed a novel design of XOR gate. This model proves designing capabilities of combinational circuits that are compatible with QCA gates within nano-scale. Novel adder circuits such as half adders, full adders, which avoid the fore, mentioned noise paths, crossovers by careful clocking organization, have been proposed. Experiment results show that the performance of proposed designs is more efficient than conventional designs. The modular layouts are verified with the freely available QCA Designer tool.