Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to abo...Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.展开更多
A low jitter All-Digital Phase-Locked Loop(ADPLL) used as a clock generator is designed.The Digital-Controlled Oscillator(DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable.Ba...A low jitter All-Digital Phase-Locked Loop(ADPLL) used as a clock generator is designed.The Digital-Controlled Oscillator(DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable.Based on the Impulse Sensitivity Function(ISF) analysis,an effective way is proposed to reduce the ADPLL's jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one.The ADPLL is implemented in a 0.18μm CMOS process with 1.8V supply voltage,occupies 0.046mm2 of on-chip area.According to the measured results,the ADPLL can operate from 108MHz to 304MHz,and the peak-to-peak jitter is 139ps when the DCO's output frequency is 188MHz.展开更多
本文在介绍了经典全数字锁相环(all digital PLL,AD-PLL)的基础上,提出了具有捕获锁定未知输入信号频率功能的ADPLL,使用方便,应用广泛。本文详尽的描述了系统的工作原理和关键部件的设计,通过计算机进行了仿真验证,并在可编程逻辑器件(...本文在介绍了经典全数字锁相环(all digital PLL,AD-PLL)的基础上,提出了具有捕获锁定未知输入信号频率功能的ADPLL,使用方便,应用广泛。本文详尽的描述了系统的工作原理和关键部件的设计,通过计算机进行了仿真验证,并在可编程逻辑器件(FPGA)中予以实现。展开更多
基金Supported by the Tsinghua National Laboratory for Information Science and Technology(TNList)Cross-Discipline Foundationthe National Science and Technology Major Project(No.2010ZX03006-003-01)
文摘Time-to-Digital Converter (TDC) is a key block used as the phase/frequency detector in an All-Digital Phase-Locked Loop (ADPLL). Usually, it occupies a large proportion of ADPLL's total power consumption up to about 30% to 40%. In this paper, the detailed power consumption of different components in the TDC is analyzed. A Power Management Block (PMB) is presented for the TDC to reduce its power consumption. A 24-bits TDC core with the proposed PMB is implemented in HJTC 0.18 μm CMOS technology. Simulation results show that up to 84% power reduction is achieved using our proposed technique.
文摘A low jitter All-Digital Phase-Locked Loop(ADPLL) used as a clock generator is designed.The Digital-Controlled Oscillator(DCO) for this ADPLL is a seven-stage ring oscillator with the delay of each stage changeable.Based on the Impulse Sensitivity Function(ISF) analysis,an effective way is proposed to reduce the ADPLL's jitter by the careful design of the sizes of the inverters used in the DCO with a simple architecture other than a complex one.The ADPLL is implemented in a 0.18μm CMOS process with 1.8V supply voltage,occupies 0.046mm2 of on-chip area.According to the measured results,the ADPLL can operate from 108MHz to 304MHz,and the peak-to-peak jitter is 139ps when the DCO's output frequency is 188MHz.
