A 5.12-GHz LC-based phase-locked loop for silicon pixel readouts of high-energy physics

There is an urgent need for high-quality and high-frequency clock generators for high-energy physics experiments.The transmission data rate exceeds 10 Gbps for a single channel in future readout electronics of silicon pixel detectors.Others,such as time measurement detectors,require a high time resolution based on the time-to-digital readout architecture.A phase-locked loop(PLL)is an essential and broadly used circuit in these applications.This study presents an application-specific integrated circuit of a low-jitter,low-power LC-tank that is PLL fabricated using 55-nm CMOS technology.It includes a 3rd-order frequency synthesis loop with a programmable bandwidth,a divide-by-2 pre-scaler,standard low-voltage differential signaling interfaces,and a current mode logic(CML)driver for clock transmissions.All the d-flip-flop dividers and phase-frequency detectors are protected from single-event upsets using the triple modular redundancy technique.The proposed VCO uses low-pass filters to suppress the noise from bias circuits.The tested LC-PLL covers a frequency locking range between 4.74 GHz and 5.92 GHz with two sub-bands.The jitter measurements of the frequency-halved clock(2.56 GHz)are less than 460 fs and 0.8 ps for the random and deterministic jitters,respectively,and a total of 7.5 ps peak-to-peak with a bit error rate of 10^(-12).The random and total jitter values for frequencies of 426 MHz and 20 MHz are less than 1.8 ps and 65 ps,respectively.The LC-PLL consumed 27 mW for the core and 73.8 mW in total.The measured results nearly coincided with the simulations and validated the analyses and tests.

Study of time resolution by digital methods with a DRS4 module

A new Digital Pulse Processing（DPP） module has been developed, based on a domino ring sampler version 4 chip（DRS4）, with good time resolution for La Br3 detectors, and different digital timing analysis methods for processing the raw detector signals are reported. The module, composed of an eight channel DRS4 chip, was used as the readout electronics and acquisition system to process the output signals from XP20D0 photomultiplier tubes（PMTs）. Two PMTs were coupled with La Br3 scintillators and placed on opposite sides of a radioactive positron22 Na source for 511 ke V γ-ray tests. By analyzing the raw data acquired by the module, the best coincidence timing resolution is about 194.7 ps（FWHM）, obtained by the digital constant fraction discrimination（d CFD） method,which is better than other digital methods and analysis methods based on conventional analog systems which have been tested. The results indicate that it is a promising approach to better localize the positron annihilation in positron emission tomography（PET） with time of flight（TOF）, as well as for scintillation timing measurement,such as in TOF-？E and TOF-E systems for particle identification, with picosecond accuracy timing measurement.Furthermore, this module is more simple and convenient than other systems.

Application of real-time digitization techniques in beam measurement for accelerators

Beam measurement is very important for accelerators. In this paper, modern digital beam measurement techniques based on I Q（In-phase ＆ Quadrature-phase） analysis are discussed. Based on this method and highspeed high-resolution analog-to-digital conversion, we have completed three beam measurement electronics systems designed for the China Spallation Neutron Source（CSNS）, Shanghai Synchrotron Radiation Facility（SSRF）, and Accelerator Driven Sub-critical system（ADS）. Core techniques of hardware design and real-time system calibration are discussed, and performance test results of these three instruments are also presented.

Beam test of CSES silicon strip detector module

The silicon-strip tracker of the China Seismo-Electromagnetic Satellite（CSES） consists of two doublesided silicon strip detectors（DSSDs） which provide incident particle tracking information.A low-noise analog ASIC VA140 was used in this study for DSSD signal readout.A beam test on the DSSD module was performed at the Beijing Test Beam Facility of the Beijing Electron Positron Collider（BEPC） using a 400–800 MeV/c proton beam.The pedestal analysis results,RMSE noise,gain correction,and intensity distribution of incident particles of the DSSD module are presented.