Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth

A reconfigurable analog baseband circuit for WLAN,WCDMA,and Bluetooth in 0.35μm CMOS is presented. The circuit consists of two variable gain amplifiers（VGA） in cascade and a Gm-C elliptic low-pass filter（LPF）. The filter-order and the cut-off frequency of the LPF can be reconfigured to satisfy the requirements of various applications. In order to achieve the optimum power consumption,the bandwidth of the VGAs can also be dynamically reconfigured and some Gm cells can be cut off in the given application.Simulation results show that the analog baseband circuit consumes 16.8 mW for WLAN,8.9 mW for WCDMA and only 6.5 mW for Bluetooth,all with a 3 V power supply.The analog baseband circuit could provide -10 to ＋40 dB variable gain,third-order low pass filtering with 1 MHz cut-off frequency for Bluetooth,fourth-order low pass filtering with 2.2 MHz cut-off frequency for WCDMA, and fifth-order low pass filtering with 11 MHz cut-off frequency for WLAN,respectively.

Analog Module Placement Design Using Genetic Algorithm

This paper presents a novel genetic algorithm for analog module placement based on a generalization of the two-dimensional bin packing problem. The genetic encoding and operators assure that all problem constraints are always satisfied. Thus the potential problems of adding penalty terms to the cost function are eliminated so that the search configuration space is drastically decreased. The dedicated cost function is based on the special requirements of analog integrated circuits. A fractional factorial experiment was conducted using an orthogonal array to study the algorithm parameters. A meta-GA was applied to determine the optimal parameter values. The algorithm was tested with several local benchmark circuits. The experimental results show that the algorithm has better performance than the simulated annealing approach with satisfactory results comparable to manual placement. This study demonstrates the effectiveness of the genetic algorithm in the analog module placement problem. The algorithm has been successfully used in a layout synthesis tool.

A multi-channel analog IC for in vitro neural recording

Recent work in the field ofneurophysiology has demonstrated that, by observing the firing characteristic of action potentials （AP） and the exchange pattern of signals between neurons, it is possible to reveal the nature of ＂memory＂ and ＂thinking＂ and help humans to understand how the brain works. To address these needs, we developed a prototype fully integrated circuit （IC） with micro-electrode array （MEA） for neural recording. In this scheme, the microelectrode array is composed by 64 detection electrodes and 2 reference electrodes. The proposed IC consists of 8 recording channels with an area of 5 x 5 mm2. Each channel can operate independently to process the neural signal by amplifying, filtering, etc. The chip is fabricated in 0.5-#m CMOS technology. The simulated and measured results show the system provides an effective device for recording feeble signal such as neural signals.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.