A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that ...A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.展开更多
In Electronic Warfare （EW） receivers, the desired Dynamic Range （DR） often far exceeds the dynamic range attainable with available Analog-to-Digital Converter （ADC） technology. ADC is the key bottleneck in achie...In Electronic Warfare （EW） receivers, the desired Dynamic Range （DR） often far exceeds the dynamic range attainable with available Analog-to-Digital Converter （ADC） technology. ADC is the key bottleneck in achieving the needed dynamic range. In this paper, an approach for improving the effective DR by utiliTing multiple amplifiers is presented. The amplifiers, arranged in parallel channels with different gains, can increase the dynamic range greatly.展开更多
A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset compo...A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm^2.展开更多
This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,th...This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.展开更多
基金Supported by the National Defense Pre-research Fund of China
文摘A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.
文摘In Electronic Warfare （EW） receivers, the desired Dynamic Range （DR） often far exceeds the dynamic range attainable with available Analog-to-Digital Converter （ADC） technology. ADC is the key bottleneck in achieving the needed dynamic range. In this paper, an approach for improving the effective DR by utiliTing multiple amplifiers is presented. The amplifiers, arranged in parallel channels with different gains, can increase the dynamic range greatly.
基金Project supported by the National High Technology Research and Development Program of China(Nos.2009AA01Z261,2009ZX01031- 003 -002 )
文摘A dual-mode analog baseband with digital-assisted DC-offset calibration （DCOC） for WCDMA/GSM receiver is presented. A digital-assisted DCOC is proposed to solve the DC-offset problem by removing the DC- offset component only. This method has no bandwidth sacrifice. After calibration the measured output residual offset voltage is within 5 mV at most gain settings and the IIP2 is more than 60 dBm. The baseband is designed to be reconfigurable at bandwidths of 200 kHz and 2.1 MHz. Total baseband gain can be programmed from 6 to 54 dB. The chip is manufactured with 0.13μm CMOS technology and consumes 10 mA from a 1.5 V supply in the GSM mode including an on-chip buffer while the core area occupies 1.2 mm^2.
文摘This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.
