A 5MS/s 12-Bit Successive Approximation Analog-to-Digital Converter

With the continuous development of science and technology, digital signal processing is more and more widely used in various fields. Among them, the analog-to-digital converter (ADC) is one of the key components to convert analog signals to digital signals. As a common type of ADC, 12-bit sequential approximation analog-to-digital converter (SAR ADC) has attracted extensive attention for its performance and application. This paper aims to conduct in-depth research and analysis of 12-bit SAR ADC to meet the growing demands of digital signal processing. This article designs a 12-bit, successive approximation analog-to-digital converter (SAR ADC) with a sampling rate of 5 MS/s. The overall circuit adopts a fully differential structure, with key modules including DAC capacitor array, comparator, and control logic. According to the DAC circuit in this paper, a fully differential capacitor DAC array structure is proposed to reduce the area of layout DAC. The comparator uses a digital dynamic comparator to improve the ADC conversion speed. The chip is designed based on the SMIC180 nm CMOS process. The simulation results show that when the sampling rate is 5 MS/s, the effective bit of SAR ADC is 11.92 bit, the SNR is 74.62 dB, and the SFDR is 89.24 dB.

Mismatch Calibration Techniques in Successive Approximation Analog-to-Digital Converters

Comparator offset cancellation and capacitor self-calibration techniques used in a successive approximation analog-to-digital converter （SA-ADC） are described. The calibration circuit works in parallel with the SAADC by adding additional calibration clock cycles to pursue high accuracy and low power consumption, and the calibrated resolution can be up to 14bit. This circuit is used in a 10bit 3Msps successive approximation ADC. This chip is realized with an SMIC 0. 18μm 1.8V process and occupies 0.25mm^2 . It consumes 3. 1mW when operating at 1.8MHz. The measured SINAD is 55. 9068dB, SFDR is 64. 5767dB, and THD is - 74. 8889dB when sampling a 320kHz sine wave.

Overview of Energy-Efficient Successive-Approximation Analog-to-Digital Converters: State-of-the-Art and a Design Example

This paper makes a review of state-of-the- arts designs of successive-approximation register analog-to-digital converters （SAR ADCs）. Methods and technique specifications are collected in view of innovative ideas. At the end of this paper, a design example is given to illustrate the procedure to design an SAR ADC. A new method, which extends the width of the internal clock, is also proposed to facilitate different sampling frequencies, which provides more time for the digital-to-analog convert （DAC） and comparator to settle. The 10 bit ADC is simulated in 0.13 μm CMOS process technology. The signal-to-noise and distortion ratio （SNDR） is 54.41 dB at a 10 MHz input with a 50 MS/s sampling rate, and the power is 330 μW.

Effect of ionizing radiation on dual 8-bit analog-to-digital converters (AD9058) with various dose rates and bias conditions

The radiation effects on several properties （reference voltage, digital output logic voltage, and supply current） of dual 8-bit analog-to-digital （A/D） converters （AD9058） under various biased conditions are investigated in this paper. Gamma ray and 10-MeV proton irradiation are selected for a detailed evaluation and comparison. Based on the measurement results induced by the gamma ray with various dose rates, the devices exhibit enhanced low dose rate sensitivity （ELDRS） under zero and working bias conditions. Meanwhile, it is obvious that the ELDRS is more severe under the working bias condition than under the zero bias condition. The degradation of AD9058 does not display obvious ELDRS during 10-MeV proton irradiation with the selected flux.

Strip silicon waveguide for code synchronization in all-optical analog-to-digital conversion based on a lumped time-delay compensation scheme

An all-optical analog-to-digital converter （ADC） based on the nonlinear effect in a silicon waveguide is a promising candidate for overcoming the limitation of electronic devices and is suitable for photonic integration. In this paper, a lumped time-delay compensation scheme with 2-bit quantization resolution is proposed. A strip silicon waveguide is designed and used to compensate for the entire time-delays of the optical pulses after a soliton self-frequency shift （SSFS） module within a wavelength range of 1550 nm-1580 nm. A dispersion coefficient as high as -19800 ps/（km.nm） with ＋0.5 ps/（km.nm） variation is predicted for the strip waveguide. The simulation results show that the maximum supportable sampling rate （MSSR） is 50.45 GSa/s with full width at half maximum （FWHM） variation less than 2.52 ps, along with the 2-bit effective- number-of-bit and Gray code output.

A 1.5 bit/s Pipelined Analog-to-Digital Converter Design with Independency of Capacitor Mismatch

A new technique which is named charge temporary storage technique (CTST) was presented to improve the linearity of a 1.5 bit/s pipelined analog-to-digital converter (ADC). The residual voltage was obtained from the sampling capacitor, and the other capacitor was just a temporary storage of charge. Then, the linearity produced by the mismatch of these capacitors was eliminated without adding extra capacitor error-averaging amplifiers. The simulation results confirmed the high linearity and low dissipation of pipelined ADCs implemented in CTST, so CTST was a new method to implement high resolution, small size ADCs.

Code synchronization based on lumped time-delay compensation scheme with a linearly chirped fiber Bragg grating in all-optical analog-to-digital conversion

We propose a novel lumped time-delay compensation scheme for all-optical analog-to-digital conversion based on soliton self-frequency shift and optical interconnection techniques. A linearly chirped fiber Bragg grating is optimally designed and used to compensate for the entire time-delays of the quantized pulses precisely. Simulation results show that the compensated coding pulses are well synchronized with a time difference less than 3.3 ps, which can support a maximum sampling rate of 151.52 GSa/s. The proposed scheme can efficiently reduce the structure complexity and cost of all-optical analog-to-digital conversion compared to the previous schemes with multiple optical time-delay lines.

A Digital Background Calibration Technique for Successive Approximation Register Analog-to-Digital Converter

A digital background calibration technique that corrects the capacitor mismatches error is proposed for successive approximation register analog-to-digital converter (SAR ADC). The technique is implemented in SAR ADC which is based on tri-level switching. The termination capacitor in the Digital-to-Analog Converter (DAC) is regarded as a reference capacitor and the digital weights of all other unit capacitors are corrected with respect to the reference capacitor. To make a comparison between the size of the unit capacitor and that of the reference capacitor, each input sample is quantized twice. The unit capacitor being calibrated is swapped with the reference capacitor during the second conversion. The difference between the two conversion results is used to correct the digital weight of the unit capacitor under calibration. The calibration technique with two reference capacitors is presented to reduce the number of parameters to be estimated. Behavior simulation is performed to verify the proposed calibration technique by using a 12-bit SAR ADC with 3% random capacitor mismatch. The simulation results show that the Signal-to-Noise and Distortion Ratio (SNDR) is improved from 57.2 dB to 72.2 dB and the Spurious Free Dynamic Range (SFDR) is improved from 60.0 dB to 85.4 dB.

Novel Optical Analog-To-Digital Converter Based on Optical Time Division Multiplexing

A novel optical analog-to-digital converter based on optical time division multiplexing(OTDM) is described which uses electrooptic sampling and time-demultiplexing together with multiple electronic analog-to-digital converter(ADC). Compared with the previous scheme, the time-division multiplexer and the time-division demultiplexer are applied in the optical analog-to-digital converter(OADC) at the same time, the design of the OADC is simplified and the performance of the OADC based on time-division demultiplexer is improved. A core optical part of the system is demonstrated with a sample rate of 10 Gs/s. The signals in three channels are demultiplexed from the optical pulses.The result proves our scheme is feasible.

Analog-to-digital conversion of information in the retina

We considered the physiological mechanisms of functioning of the retina’s neural network. It is marked that the primary function of a neural network is an analog-to-digital conversion of the receptor potential of photoreceptor into the pulse-to-digital signal to ganglion cells. We showed the role of different types of neurons in the work of analog-to-digital converter. We gave the equivalent circuit of this converter. We researched the mechanism of the numeric coding of the receptor potential of the photoreceptor.

基于RESYS程序的TOPAZ-Ⅱ反应堆系统模拟

本文使用C++语言开发了面向先进核反应堆的通用反应堆系统分析程序RESYS,在该程序的基础上建立了热离子核反应堆电源TOPAZ-Ⅱ的模型,并对其启动瞬态和稳态工况进行了模拟。建立的TOPAZ-Ⅱ反应堆系统模型包括反应堆堆芯热工模型、热离子静态热电转换系统模型、热排放辐射散热器模型。铯热离子转换器电流密度使用Rasor模型,并使用6组缓发中子点堆动力学模型计算反应堆堆芯裂变功率随时间的变化,考虑各结构部件对反应性的影响。计算得到的稳态电功率输出与TITAM程序的计算结果较为一致,反应堆系统热电转换效率为5.04%。计算结果验证了所开发的RESYS程序以及建立的TOPAZ-Ⅱ系统模型的正确性。

Principle, Modeling and Control of DC-DC Convertors for EV

DC DC convertors can convert the EV's high voltage DC power supply into the low voltage DC power supply. In order to design an excellent convertor one must be guided by theory of automatic control. The principle and the method of design, modeling and control for DC DC convertors of EV are introduced. The method of the system response to a unit step function input and the frequency response method are applied to researching the convertor's mathematics model and control characteristic. Experiments show that the designed DC DC convertor's output voltage precision is high, the antijamming ability is strong and the adjustable performance is fast and smooth.

智能化转炉干法除尘水汽柔性调节装置

面对我国日益严峻的环保形势,为满足转炉烟气超低排放的要求,通过分析转炉一次烟气干法除尘的工艺流程和设备原理,研发了配置有柔性调节装置的转炉一次烟气干法除尘新工艺。柔性调节装置采用了智能化调节控制系统,通过其自有的水汽调节装置实时分析转炉状态,智能化地适应转炉的不同冶炼状态,并能及时切换运行模式。生产实践表明,柔性调节装置结构合理,安全可靠,新工艺能有效解决企业在控制成本前提下对转炉一次烟气超低排放的问题,满足环保排放指标要求的同时节约成本。

海上风电柔性直流技术研究进展与展望

本文概述了全球海上风电发展情况,从政策、规划、资源、技术角度分析了我国海上风电发展的宏观基本面。详细介绍了国内外海上风电柔性直流送出的主流技术路线和技术发展现状。针对几类新型海上风电柔直系统拓扑结构,从技术、经济性方面进行了综合比较分析,并对其工程应用潜力进行了研判。最后提出了我国海上风电柔性直流技术研究与创新发展的战略思考和建议。

特高压换流站监视云边协同计算优化研究

随着我国特高压电力系统的不断发展,特高压换流站中需要实时测量的数据呈现指数增长。针对现有保护系统数据传输不能满足数据采集实时性要求的问题,提出一种云边协同的计算架构。首先,对特高压换流站内的数据采集问题进行建模,并证明最优通信调度与计算资源分配问题是一个凹优化问题。其次,提出一种云边协同通信调度与计算资源分配方法,对具有严格延迟界限的任务在边缘从站处理,而具有宽松延迟界限的任务被传输到云端主站,实现特高压换流站中传感器数据的低传输延时通信调度与计算资源分配。仿真模拟表明采用所提方法可以使特高压换流站内通信满足任务延迟要求的概率提高了14%到30%,提高了数据传输效率。

微电网V2G双向变换器运行状态分析方法

针对现有微电网V2G双向变换器运行数据的智能监测系统抗干扰性差、监测精度低等问题,提出一种新型配电自动化监测系统架构。该系统采用集成模拟电路的实时配电系统状态估计器(distribution system state estimator,DSSE)作为监测系统的关键部件。开发的DSSE针对配微电网V2G双向变换器监测系统进行了单元优化,在变电站实时执行监控,可通过多区域状态估计算法进行协调,提高监控事件的时间效率和鲁棒性,同时也保持了可接受的精度水平。设计了针对虚假噪声信号注入防护的试验,试验结果表明,该系统对于这类攻击具有较高稳定性,能有效保护微电网V2G双向变换器运行数据的质量。

某船电源转换装置对电网绝缘监测干涉原因分析

配电板和交流不间断电源装置为电源转换装置提供主用、备用两路电源输入,简单的供电关系却造成了某船电源转换装置对电网绝缘监测干涉的现象。通过对干涉现象分析,结合设备之间的内在联系和电源转换装置两路电源转换原理以及绝缘监测的工作原理,找到固态开关的两路电源转换是造成干涉现象的根源,通过试验验证,提出可行的解决方案。

Multi-narrowband signals receiving method based on analog-to-information convertor and block sparsity

The analog-to-information convertor (AIC) is a successful practice of compressive sensing (CS) theory in the analog signal acquisition. This paper presents a multi-narrowband signals sampling and reconstruction model based on AIC and block sparsity. To overcome the practical problems, the block sparsity is divided into uniform block and non-uniform block situations, and the block restricted isometry property and sub-sampling limit in different situations are analyzed respectively in detail. Theoretical analysis proves that using the block sparsity in AIC can reduce the restricted isometric constant, increase the reconstruction probability and reduce the sub -sampling rate. Simulation results show that the proposed model can complete sub -sampling and reconstruction for multi-narrowband signals. This paper extends the application range of AIC from the finite information rate signal to the multi-narrowband signals by using the potential relevance of support sets. The proposed receiving model has low complexity and is easy to implement, which can promote the application of CS theory in the radar receiver to reduce the burden of analog-to digital convertor (ADC) and solve bandwidth limitations of ADC.

动态响应误差驱动的风机并网变流器控制参数辨识方法

为了获取更精准的双馈风机变流器暂态模型参数,保障风力发电联网运行仿真分析结果的准确性,满足新能源高占比电力系统的安全稳定运行要求,文中提出了一种输出响应误差驱动的参数辨识方法。根据双馈风机的机电暂态模型确定出待辨识的参数,实现了MATLAB与PSASP的循环调用,根据真实值下的动态响应曲线与辨识值下的动态响应曲线的误差最小来确定最终辨识值,并通过设置不同工况验证该辨识方法的有效性。

电爆桥膜换能元设计研究

基于国内外电爆桥膜换能元技术的研究现状,总结了桥膜换能元的基本结构和类型,给出了V形桥区电阻和质量的计算方法;并提出了电容放电输入和长脉冲恒流输入条件下桥膜换能元的电热致电爆换能模型,以便估算桥膜换能元温升及临界爆发参数。采用溅射镀膜方法制备了多种不同结构的桥膜芯片及其桥塞换能元,测试表明桥膜芯片的电阻偏差均小于±5%。电爆实验表明,电阻/质量为2.25Ω/0.196μg的芯片与Φ3.4mm的桥塞所集成的换能元,在24V/33μF放电下的爆发时间为87μs,瞬发度很高;5min恒流脉冲输入的不爆发电流约为0.91A,电流安全性较好。电阻/质量分别为1.03Ω/0.259μg和1.05Ω/0.095μg的芯片与Φ3.4mm的桥塞所集成的换能元,5min恒流脉冲输入的不爆发电流均大于1.32A,电流安全性较高。