In this paper we investigate simultaneous approximation for arbitrary system of nodes on smooth domain in complex plane. Some results which are better than those of known theorems are obtained.
In this paper, supose Γ be a boundary of a Jordan domain D and Γ satisfied Альпер condition, the order that rational type interpolating operators at Fejer's points of f(z)∈C(Γ) converge to f(z) in the se...In this paper, supose Γ be a boundary of a Jordan domain D and Γ satisfied Альпер condition, the order that rational type interpolating operators at Fejer's points of f(z)∈C(Γ) converge to f(z) in the sense of uniformly convergence is obtained.展开更多
This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, e...This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, especially for wireless sensor network（WSN） applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits（ENOB） of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity（DNL） is less than 0.83 LSB and the integral nonlinearity（INL） is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm^2.展开更多
文摘In this paper we investigate simultaneous approximation for arbitrary system of nodes on smooth domain in complex plane. Some results which are better than those of known theorems are obtained.
文摘In this paper, supose Γ be a boundary of a Jordan domain D and Γ satisfied Альпер condition, the order that rational type interpolating operators at Fejer's points of f(z)∈C(Γ) converge to f(z) in the sense of uniformly convergence is obtained.
基金supported by the PhD Programs Foundation of the Ministry of Education of China(No.20111011315)the National Science and Technology Important Project of China(No.2010ZX03006-003-01)
文摘This paper presents a 6-bit 20-MS/s high spurious-free dynamic range（SFDR） and low power successive approximation register analog to digital converter（SAR ADC） for the radio-frequency（RF） transceiver frontend, especially for wireless sensor network（WSN） applications.This ADC adopts the modified common-centroid symmetry layout and the successive approximation register reset circuit to improve the linearity and dynamic range. Prototyped in a 0.18-μm 1P6M CMOS technology,the ADC performs a peak SFDR of 55.32 dB and effective number of bits（ENOB） of 5.1 bit for 10 MS/s.At the sample rate of 20 MS/s and the Nyquist input frequency,the 47.39-dB SFDR and 4.6-ENOB are achieved.The differential nonlinearity（DNL） is less than 0.83 LSB and the integral nonlinearity（INL） is less than 0.82 LSB.The experimental results indicate that this SAR ADC consumes a total of 522μW power and occupies 0.98 mm^2.
