Novel lateral insulated gate bipolar transistor on SOI substrate for optimizing hot-carrier degradation

A novel lateral insulated gate bipolar transistor on a silicon-on-insulator substrate SOI-LIGBT with a special low-doped P-well structure is proposed.The P-well structure is added to attach the P-body under the channel so as to reduce the linear anode current degradation without additional process.The influence of the length and depth of the P-well on the hot-carrier HC reliability of the SOI-LIGBT is studied.With the increase in the length of the P-well the perpendicular electric field peak and the impact ionization peak diminish resulting in the reduction of the hot-carrier degradation. In addition the impact ionization will be weakened with the increase in the depth of the P-well which also makes the hot-carrier degradation decrease.Considering the effect of the low-doped P-well and the process windows the length and depth of the P-well are both chosen as 2 μm.

A novel high-voltage light punch-through carrier stored trench bipolar transistor with buried p-layer

A novel high-voltage light punch-through（LPT） carrier stored trench bipolar transistor（CSTBT） with buried p-layer（BP） is proposed in this paper.Since the negative charges in the BP layer modulate the bulk electric field distribution,the electric field peaks both at the junction of the p base/n-type carrier stored（N-CS） layer and the corners of the trench gates are reduced,and new electric field peaks appear at the junction of the BP layer/N drift region.As a result,the overall electric field in the N drift region is enhanced and the proposed structure improves the breakdown voltage（BV） significantly compared with the LPT CSTBT.Furthermore,the proposed structure breaks the limitation of the doping concentration of the N-CS layer（NN CS） to the BV,and hence a higher NN CS can be used for the proposed LPT BP-CSTBT structure and a lower on-state voltage drop（Vce（sat）） can be obtained with almost constant BV.The results show that with a BP layer doping concentration of NBP = 7 × 10^15 cm^-3,a thickness of LBP = 2.5 μm,and a width of WBP = 5 μm,the BV of the proposed LPT BP-CSTBT increases from 1859 V to 1862 V,with NN CS increasing from 5 × 10^15 cm^-3 to 2.5 × 10^16 cm^-3.However,with the same N-drift region thickness of 150 μm and NN CS,the BV of the CSTBT decreases from 1598 V to 247 V.Meanwhile,the Vce（sat） of the proposed LPT BP-CSTBT structure decreases from 1.78 V to 1.45 V with NN CS increasing from 5 × 10^15 cm^-3 to 2.5 × 10^16 cm^-3.

A G-band terahertz monolithic integrated amplifier in 0.5-μm InP double heterojunction bipolar transistor technology

Design and characterization of a G-band（140–220 GHz） terahertz monolithic integrated circuit（TMIC） amplifier in eight-stage common-emitter topology are performed based on the 0.5-μm In Ga As/In P double heterojunction bipolar transistor（DHBT）. An inverted microstrip line is implemented to avoid a parasitic mode between the ground plane and the In P substrate. The on-wafer measurement results show that peak gains are 20 dB at 140 GHz and more than 15-dB gain at 140–190 GHz respectively. The saturation output powers are-2.688 dBm at 210 GHz and-2.88 dBm at 220 GHz,respectively. It is the first report on an amplifier operating at the G-band based on 0.5-μm InP DHBT technology. Compared with the hybrid integrated circuit of vacuum electronic devices, the monolithic integrated circuit has the advantage of reliability and consistency. This TMIC demonstrates the feasibility of the 0.5-μm InGaAs/InP DHBT amplifier in G-band frequencies applications.

Comparison of total dose effects on SiGe heterojunction bipolar transistors induced by different swift heavy ion irradiation

The degradations in NPN silicon-germanium （SiGe） heterojunction bipolar transistors （HBTs） were fully studied in this work, by means of 25-MeV Si, 10-MeV C1, 20-MeV Br, and 10-MeV Br ion irradiation, respectively. Electrical parameters such as the base current （IB）, current gain （β）, neutral base recombination （NBR）, and Early voltage （VA） were investigated and used to evaluate the tolerance to heavy ion irradiation. Experimental results demonstrate that device degradations are indeed radiation-source-dependent, and the larger the ion nuclear energy loss is, the more the displacement damages are, and thereby the more serious the performance degradation is. The maximum degradation was observed in the transistors irradiated by 10-MeV Br. For 20-MeV and 10-MeV Br ion irradiation, an unexpected degradation in Ic was observed and Early voltage decreased with increasing ion fluence, and NBR appeared to slow down at high ion fluence. The degradations in SiGe HBTs were mainly attributed to the displacement damages created by heavy ion irradiation in the transistors. The underlying physical mechanisms are analyzed and investigated in detail.

Development of 8-inch Key Processes for Insulated-Gate Bipolar Transistor

Based on the construction of the 8-inch fabricat ion line, advanced process technology of 8-inch wafer, as well as the fourth-generation high-voltage double-diffused metal-oxide semiconductor(DMOS+) insulated-gate bipolar transistor(IGBT) technology and the fifth-generation trench gate IGBT technology, have been developed, realizing a great-leap forward technological development for the manufacturing of high-voltage IGBT from 6-inch to 8-inch. The 1600 A/1.7 kV and 1500 A/3.3 kV IGBT modules have been successfully fabricated, qualified, and applied in rail transportation traction system.

Early effect modeling of silicon-on-insulator SiGe heterojunction bipolar transistors

Silicon germanium （SiGe） heterojunction bipolar transistor （HBT） on thin silicon-on-insulator （SOI） has recently been demonstrated and integrated into the latest SOI BiCMOS technology. The Early effect of the SOI SiGe HBT is analysed considering vertical and horizontal collector depletion, which is different from that of a bulk counterpart. A new compact formula of the Early voltage is presented and validated by an ISE TCAD simulation. The Early voltage shows a kink with the increase of the reverse base-collector bias. Large differences are observed between SOI devices and their bulk counterparts. The presented Early effect model can be employed for a fast evaluation of the Early voltage and is useful to the design, the simulation and the fabrication of high performance SOI SiCe devices and circuits.

Analytical base collector depletion capacitance in vertical SiGe heterojunction bipolar transistors fabricated on CMOS-compatible silicon on insulator

The base-collector depletion capacitance for vertical SiGe npn heterojunction bipolar transistors （HBTs） on silicon on insulator （SOI） is split into vertical and lateral parts. This paper proposes a novel analytical depletion capacitance model of this structure for the first time. A large discrepancy is predicted when the present model is compared with the conventional depletion model, and it is shown that the capacitance decreases with the increase of the reverse collector- base bias-and shows a kink as the reverse collector-base bias reaches the effective vertical punch-through voltage while the voltage differs with the collector doping concentrations, which is consistent with measurement results. The model can be employed for a fast evaluation of the depletion capacitance of an SOI SiGe HBT and has useful applications on the design and simulation of high performance SiGe circuits and devices.

Thermal stability improvement of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations using non-uniform finger spacing

A method of non-uniform finger spacing is proposed to enhance thermal stability of a multiple finger power SiGe heterojunction bipolar transistor under different power dissipations. Temperature distribution on the emitter fingers of a multi-finger SiGe heterojunction bipolar transistor is studied using a numerical electro-thermal model. The results show that the SiGe heterojunction bipolar transistor with non-uniform finger spacing has a small temperature difference between fingers compared with a traditional uniform finger spacing heterojunction bipolar transistor at the same power dissipation. What is most important is that the ability to improve temperature non-uniformity is not weakened as power dissipation increases. So the method of non-uniform finger spacing is very effective in enhancing the thermal stability and the power handing capability of power device. Experimental results verify our conclusions.

Substrate bias effects on collector resistance in SiGe heterojunction bipolar transistors on thin film silicon-on-insulator

An analytical expression for the co/lector resistance of a novel vertical SiGe heterojunction bipolar transistor （HBT） on thin film silicon-on-insulator （SOI） is obtained with the substrate bias effects being considered. The resistance is found to decrease slowly and then quickly and to have kinks with the increase of the substrate-collector bias, which is quite different from that of a conventional bulk HBT. The model is consistent with the simulation result and the reported data and is useful to the frequency characteristic design of 0.13 μtm millimeter-wave SiGe SOI BiCMOS devices.

Common Base Four-Finger InGaAs/InP Double Heterojunction Bipolar Transistor with Maximum Oscillation Frequency 535 GHz

A common base four-finger InOaAs/InP double heterojunction bipolar transistor with 535 OHz fmax by using the 0.5 μm emitter technology is fabricated. Multi-finger design is used to increase the input current. Common base configuration is compared with common emitter configuration, and shows a smaller K factor at high frequency span, indicating a larger breakpoint frequency of maximum stable gain/maximum available gain （MSG/MAG） and thus a higher gain near the cut-off frequency, which is useful in THz amplifier design.

A dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor on a silicon-on-insulator substrate

In this paper, a novel dual-gate and dielectric-inserted lateral trench insulated gate bipolar transistor （DGDI LTIGBT） structure, which features a double extended trench gate and a dielectric inserted in the drift region, is proposed and discussed. The device can not only decrease the specific on-resistance Ron,sp , but also simultaneously improve the temperature performance. Simulation results show that the proposed LTIGBT achieves an ultra-low on-state voltage drop of 1.31 V at 700 A·cm-2 with a small half-cell pitch of 10.5 μm, a specific on-resistance R on,sp of 187 mΩ·mm2, and a high breakdown voltage of 250 V. The on-state voltage drop of the DGDI LTIGBT is 18% less than that of the DI LTIGBT and 30.3% less than that of the conventional LTIGBT. The proposed LTIGBT exhibits a good positive temperature coefficient for safety paralleling to handling larger currents and enhances the short-circuit capability while maintaining a low self-heating effect. Furthermore, it also shows a better tradeoff between the specific on-resistance and the turnoff loss, although it has a longer turnoff delay time.

A single-event transient induced by a pulsed laser in a silicon-germanium heterojunction bipolar transistor

A study on the single event transient （SET） induced by a pulsed laser in a silicon-germanium （SiGe） heterojunction bipolar transistor （HBT） is presented in this work. The impacts of laser energy and collector load resistance on the SET are investigated in detail. The waveform, amplitude, and width of the SET pulse as well as collected charge are used to characterize the SET response. The experimental results are discussed in detail and it is demonstrated that the laser energy and load resistance significantly affect the SET in the SiGe HBT. Furthermore, the underlying physical mechanisms are analyzed and investigated, and a near-ideal exponential model is proposed for the first time to describe the discharge of laser-induced electrons via collector resistance to collector supply when both base-collector and collector-substrate junctions are reverse biased or weakly forward biased. Besides, it is found that an additional multi-path discharge would play an important role in the SET once the base-collector and collector-substrate junctions get strongly forward biased due to a strong transient step charge by the laser pulse.

Insulated gate bipolar transistor inverter for arc welding

This paper introduces the Insulated gate bipolar transistor(IGBT)in- verter for arc welding.The principle of the inverter,the structure and charac- teristics of IGBT and the current feedback system using LEM current transduc- er are discussed.By the measurement of its efficiency and power factor and the tests of welding processes,the developed 150A IGBT inverter proves to be a kind of energy-saving portable power supply for arc welding with broad prospects.

Physical modeling based on hydrodynamic simulation for the design of InGaAs/InP double heterojunction bipolar transistors

A physical model for scaling and optimizing InGaAs/InP double heterojunction bipolar transistors（DHBTs） based on hydrodynamic simulation is developed.The model is based on the hydrodynamic equation,which can accurately describe non-equilibrium conditions such as quasi-ballistic transport in the thin base and the velocity overshoot effect in the depleted collector.In addition,the model accounts for several physical effects such as bandgap narrowing,variable effective mass,and doping-dependent mobility at high fields.Good agreement between the measured and simulated values of cutoff frequency,f t,and maximum oscillation frequency,f max,are achieved for lateral and vertical device scalings.It is shown that the model in this paper is appropriate for downscaling and designing InGaAs/InP DHBTs.

Laser-Induced Single Event Transients in Local Oxidation of Silicon and Deep Trench Isolation Silicon-Germanium Heterojunction Bipolar Transistors

We present a study on the single event transient （SET） induced by a pulsed laser in different silicon-germanium （SiGe） heterojunction bipolar transistors （HBTs） with the structure of local oxidation of silicon （LOCOS） and deep trench isolation （DTI）. The experimental results are discussed in detail and it is demonstrated that a SiGe HBT with the structure of LOCOS is more sensitive than the DTI SiGe HBT in the SET. Because of the limitation of the DTI structure, the charge collection of diffusion in the DTI SiGe HBT is less than that of the LOCOS SiGe HBT. The SET sensitive area of the LOCOS SiGe HBT is located in the eollector-substrate （C/S） junction, while the sensitive area of the DTI SiGe HBT is located near to the collector electrodes.

Angular dependence of proton-induced single event transient in silicon-germanium heterojunction bipolar transistors

We investigate the angular dependence of proton-induced single event transient(SET) in silicon-germanium heterojunction bipolar transistors. Experimental results show that the overall SET cross section is almost independent of proton incident angle. However, the proportion of SET events with long duration and high integral charge collection grows significantly with the increasing angle. Monte Carlo simulations demonstrate that the integral cross section of proton incident events with high ionizing energy deposition in the sensitive volume tends to be higher at larger incident angles, which is associated with the angular distribution of proton-induced secondary particles and the geometry of sensitive volume.

Neuro-Space Mapping for Modeling Heterojunction Bipolar Transistor

A neuro-space mapping(Neuro-SM) for modeling heterojunction bipolar transistor(HBT) is presented, which can automatically modify the input signals of the given model by neural network. The novel Neuro-SM formulations for DC and small-signal simulation are proposed to obtain the mapping network. Simulation results show that the errors between Neuro-SM models and the accurate data are less than 1%, demonstrating that the accurcy of the proposed method is higher than those of the existing models.

Modeling and Simulation of Photoelectronic Lambda Bipolar Transistor

Based on the region model of lambda bipolar transistor ( LBT), a dividing region theory model of PLBT is set up,simulated and verified. Firstly, the principal operations of different kinds of photoelectronic lambda bipolar transistor ( PLBT) are characterized by a simple circuit model. Through mathematical analysis of the equivalent circuit, the typical characteristics curve is divided into positive resistance, peak, negative resistance and cutoff regions. Secondly, by analyzing and simulating this model, the ratio of MOSFET width to channel length, threshold voltage and common emitter gain are discovered as the main structure parameters that determine the characteristic curves of PLBT. And peak region width, peak current value, negative resistance value and valley voltage value of PLBT can be changed conveniently according to the actual demands by modifying these parameters. Finally comparisons of the characteristics of the fabricated devices and the simu- lation results are made, which show that the analytical results are in agreement with the observed devices characteristics.

Heavy Ion and Laser Microbeam Induced Current Transients in SiGe Heterojunction Bipolar Transistor

Silicon-germanium （SiGe） hereto-junction bipolar transistor current transients induced by pulse laser and heavy iron are measured using a real-time digital oscilloscope. These transients induced by pulse laser and heavy iron exhibit the same waveform and charge collection time except for the amplitude of peak current. Different laser energies and voltage biases under heavy ion irradiation also have impact on current transient, whereas the waveform remains unchanged. The position-correlated current transients suggest that the nature of the current transient is controlled by the behavior of the C/S junction.

A device model for thin silicon-on-insulator SiGe heterojunction bipolar transistors with saturation effects

In this paper, we describe the saturation effect of a silicon germanium （SiGe） heterojunction bipolar transistor （HBT） fabricated on a thin silicon-on-insulator （SOI） with a step-by-step derivation of the model formulation. The collector injection width, the internal base-collector bias, and the hole density at the base-collector junction interface are analysed by considering the unique features of the internal and the external parts of the collector, as they are different from those of a bulk counterpart.