Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic t...Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.展开更多
针对多时钟数字系统提出了一种新颖的产生测试矢量的方法——安全充分捕获技术(Safe and CompleteCapture Technology,S&CCT).该方法对电路系统中的时钟按照一定的标准分为等效时钟和串行时钟,然后确定正确的时钟捕获顺序.使用并发...针对多时钟数字系统提出了一种新颖的产生测试矢量的方法——安全充分捕获技术(Safe and CompleteCapture Technology,S&CCT).该方法对电路系统中的时钟按照一定的标准分为等效时钟和串行时钟,然后确定正确的时钟捕获顺序.使用并发故障模拟器从逻辑上和时序上对生成的测试矢量进行仿真,测试矢量生成器使用该仿真信息,以避免生成失效测试矢量.实验证明,S&CCT与传统方法相比,测试矢量数目减少50%左右,不仅大大减少了测试矢量的数目,对电路的硬件开销也几乎没有影响.展开更多
Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation.Techniques based on partial maximum satisfiability are often used to track man...Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation.Techniques based on partial maximum satisfiability are often used to track many hard problems in various domains,including artificial intelligence,computational biology,data mining,and machine learning.We observe that part of the test patterns generated by the commercial Automatic Test Pattern Generation(ATPG)tool is redundant,and the relationship between test patterns and faults,as a significant information,can effectively induce the test patterns reduction process.Considering a test pattern can detect one or more faults,we map the problem of static test compaction to a partial maximum satisfiability problem.Experiments on ISCAS89,ISCAS85,and ITC99 benchmarks show that this approach can reduce the initial test set size generated by TetraMAX18 while maintaining fault coverage.展开更多
A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one ...A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one is able to test a digital circuit automatically. The user interface of the logic analyzer was programmed with LabVIEW. Two Arduino UNO boards were used as the hardware targets to input and output the logic signals. The maximum pattern update rate was set to be 20 Hz. The maximum logic sampling rate was set to be 200 Hz. After twelve thousand cycles of exhaustive tests,the logic analyzer had a 100% accuracy. As a tutorial showing how to build virtual instruments with Arduino,the software detail is also explained in this article.展开更多
文摘Advancements in semiconductor technology are making gate-level test generation more challenging. This is because a large amount of detailed structural information must be processed in the search process of automatic test pattern generation (ATPG). In addition, ATPG needs to deal with new defects caused by process variation when IC is shrinking. To reduce the computation effort of ATPG, test generation could be started earlier at higher abstraction level, which is in line with top-down design methodology that has become more popular nowadays. In this research, we employ Chen’s high-level fault model in the high-level ATPG. Besides shorter ATPG time as shown in many previous works, our study showed that high-level ATPG also contributes to test compaction. This is because most of the high-level faults correlate with the gate-level collapsed faults especially at input/output of the modules in a circuit. The high-level ATPG prototype used in our work is mainly composed by constraint-driven test generation engine and fault simulation engine. Experimental result showed that more reduced/compact test set can be generated from the high-level ATPG.
基金supported by Hi-Tech Research and Development Program of China(2007AA01Z109)the National Natural Science Foundation of China(60633060)by the National Basic Research Program of China (973)(2005CB321604)
文摘针对多时钟数字系统提出了一种新颖的产生测试矢量的方法——安全充分捕获技术(Safe and CompleteCapture Technology,S&CCT).该方法对电路系统中的时钟按照一定的标准分为等效时钟和串行时钟,然后确定正确的时钟捕获顺序.使用并发故障模拟器从逻辑上和时序上对生成的测试矢量进行仿真,测试矢量生成器使用该仿真信息,以避免生成失效测试矢量.实验证明,S&CCT与传统方法相比,测试矢量数目减少50%左右,不仅大大减少了测试矢量的数目,对电路的硬件开销也几乎没有影响.
基金supported by the National Natural Science Foundation of China(Nos.61672261 and 61872159)。
文摘Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation.Techniques based on partial maximum satisfiability are often used to track many hard problems in various domains,including artificial intelligence,computational biology,data mining,and machine learning.We observe that part of the test patterns generated by the commercial Automatic Test Pattern Generation(ATPG)tool is redundant,and the relationship between test patterns and faults,as a significant information,can effectively induce the test patterns reduction process.Considering a test pattern can detect one or more faults,we map the problem of static test compaction to a partial maximum satisfiability problem.Experiments on ISCAS89,ISCAS85,and ITC99 benchmarks show that this approach can reduce the initial test set size generated by TetraMAX18 while maintaining fault coverage.
文摘A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one is able to test a digital circuit automatically. The user interface of the logic analyzer was programmed with LabVIEW. Two Arduino UNO boards were used as the hardware targets to input and output the logic signals. The maximum pattern update rate was set to be 20 Hz. The maximum logic sampling rate was set to be 200 Hz. After twelve thousand cycles of exhaustive tests,the logic analyzer had a 100% accuracy. As a tutorial showing how to build virtual instruments with Arduino,the software detail is also explained in this article.
