System Supporting Automatic Generation of Finite Element Using Image Information

A mesh generating system has been developed in orde r to prepare large amounts of input data which are needed for easy implementation of a finite element analysis. This system consists of a Pre-Mesh Generator, an Automatic Mesh Generator and a Mesh Modifier. Pre-Mesh Generator produces the shape and sub-block information as input data of Automatic Mesh Generator by c arrying out various image processing with respect to the image information of th e drawing input using scanner. Automatic Mesh Generator generates mesh of trian gular elements in the arbitrarily shaped and multiple connected planar domain by using minimum necessary information. This generator has 3 methods of mesh gene ration for each sub-block, A) Regular Mesh Generation, B) Semi-Regular Mesh Ge neration and C) Irregular Mesh Generation. Any of them can be selected automati cally according to the external form of sub-block or the state of domain. Mesh Modifier projects and modifies the pattern of generated mesh by Automatic Mesh Generator as required. This system simplifies the user’s task while saving manp ower in carrying out the finite element analysis.

Automatic Target Description File Generation

Agile hardware design is gaining increasing momentum and bringing new chips in larger quantities to the market faster.However,it also takes new challenges for compiler developers to retarget existing compilers to these new chips in shorter time than ever before.Currently,retargeting a compiler backend,e.g.,an LLVM backend to a new target,requires compiler developers to write manually a set of target description files(totalling 10300+lines of code(LOC)for RISC-V in LLVM),which is error-prone and time-consuming.In this paper,we introduce a new approach,Au-tomatic Target Description File Generation(ATG),which accelerates the generation of a compiler backend for a new tar-get by generating its target description files automatically.Given a new target,ATG proceeds in two stages.First,ATG synthesizes a small list of target-specific properties and a list of code-layout templates from the target description files of a set of existing targets with similar instruction set architectures(ISAs).Second,ATG requests compiler developers to fill in the information for each instruction in the new target in tabular form according to the list of target-specific properties syn-thesized and then generates its target description files automatically according to the list of code-layout templates synthe-sized.The first stage can often be reused by different new targets sharing similar ISAs.We evaluate ATG using nine RISC-V instruction sets drawn from a total of 1029 instructions in LLVM 12.0.ATG enables compiler developers to gen-erate compiler backends for these ISAs that emit the same assembly code as the existing compiler backends for RISC-V but with significantly less development effort(by specifying each instruction in terms of up to 61 target-specific properties only).