A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one ...A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one is able to test a digital circuit automatically. The user interface of the logic analyzer was programmed with LabVIEW. Two Arduino UNO boards were used as the hardware targets to input and output the logic signals. The maximum pattern update rate was set to be 20 Hz. The maximum logic sampling rate was set to be 200 Hz. After twelve thousand cycles of exhaustive tests,the logic analyzer had a 100% accuracy. As a tutorial showing how to build virtual instruments with Arduino,the software detail is also explained in this article.展开更多
Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation.Techniques based on partial maximum satisfiability are often used to track man...Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation.Techniques based on partial maximum satisfiability are often used to track many hard problems in various domains,including artificial intelligence,computational biology,data mining,and machine learning.We observe that part of the test patterns generated by the commercial Automatic Test Pattern Generation(ATPG)tool is redundant,and the relationship between test patterns and faults,as a significant information,can effectively induce the test patterns reduction process.Considering a test pattern can detect one or more faults,we map the problem of static test compaction to a partial maximum satisfiability problem.Experiments on ISCAS89,ISCAS85,and ITC99 benchmarks show that this approach can reduce the initial test set size generated by TetraMAX18 while maintaining fault coverage.展开更多
This paper first establishes a neural network model for logic circuits fromthe truth table by using linear equations theory, presents a kind of ATPG neuralnetwork model, and investigates energy local minima for the ne...This paper first establishes a neural network model for logic circuits fromthe truth table by using linear equations theory, presents a kind of ATPG neuralnetwork model, and investigates energy local minima for the network- And then,it proposes the corresponding techniques to reduce the number of energy localminima as well as some approaches to escaping from local minimum of eliergyFinally, two simulation systems, the binary ATPG neural network and thecontinuous ATPG neural network, are implemented oli SUN 3/260 workstationin C language. The experimental results and their analysis and discussion aregiven. The preliminary experimental results show that this method is feasibleand promising.展开更多
文摘A simple,stable and reliable virtual logic analyzer is presented. The logic analyzer had two modules:one was the test pattern generation module,the other was the logic monitoring module. Combining the two modules,one is able to test a digital circuit automatically. The user interface of the logic analyzer was programmed with LabVIEW. Two Arduino UNO boards were used as the hardware targets to input and output the logic signals. The maximum pattern update rate was set to be 20 Hz. The maximum logic sampling rate was set to be 200 Hz. After twelve thousand cycles of exhaustive tests,the logic analyzer had a 100% accuracy. As a tutorial showing how to build virtual instruments with Arduino,the software detail is also explained in this article.
基金supported by the National Natural Science Foundation of China(Nos.61672261 and 61872159)。
文摘Static compaction methods aim at finding unnecessary test patterns to reduce the size of the test set as a post-process of test generation.Techniques based on partial maximum satisfiability are often used to track many hard problems in various domains,including artificial intelligence,computational biology,data mining,and machine learning.We observe that part of the test patterns generated by the commercial Automatic Test Pattern Generation(ATPG)tool is redundant,and the relationship between test patterns and faults,as a significant information,can effectively induce the test patterns reduction process.Considering a test pattern can detect one or more faults,we map the problem of static test compaction to a partial maximum satisfiability problem.Experiments on ISCAS89,ISCAS85,and ITC99 benchmarks show that this approach can reduce the initial test set size generated by TetraMAX18 while maintaining fault coverage.
文摘This paper first establishes a neural network model for logic circuits fromthe truth table by using linear equations theory, presents a kind of ATPG neuralnetwork model, and investigates energy local minima for the network- And then,it proposes the corresponding techniques to reduce the number of energy localminima as well as some approaches to escaping from local minimum of eliergyFinally, two simulation systems, the binary ATPG neural network and thecontinuous ATPG neural network, are implemented oli SUN 3/260 workstationin C language. The experimental results and their analysis and discussion aregiven. The preliminary experimental results show that this method is feasibleand promising.
