SiGe-based thermoelectric(TE)materials have gained increasing interests due to their low maintenance costs,environmental friendliness and long lifespan.However,the intrinsically high thermal conductivity of Si-based m...SiGe-based thermoelectric(TE)materials have gained increasing interests due to their low maintenance costs,environmental friendliness and long lifespan.However,the intrinsically high thermal conductivity of Si-based materials also results in poor TE properties.In this investigation,a zirconia(ZrO_(2))composite strategy was applied to an n-type SiGe alloy,tremendously elevating its TE performance.After mechanical alloying and spark plasma sintering(SPS)processes,the ZrO_(2)induced the formation of nanopores in the SiGe matrix via phosphorus adsorption.Moreover,such increase in porosity enhanced the phonon scattering and dramatically suppressed lattice thermal conductivity,from 2.83 to 1.59 W·m^(-1)·K^(-1)at 873 K.Additionally,reduced phosphorus doping led to an increase in Seebeck coefficients and a relatively minor decrease in electrical conductivity,The power factor didn't deteriorate significantly,either,as its maximum of~3.43 mW·m^(-1-)K^(-2)was achieved at 873 K with(Si_(0.8)Ge_(0.2))_(0.097)P_(0.03)(ZrO_(2))_(0.003).In short,a peak figure of merit(ZT)of~1.27 at 873 K and an average ZT~0.7 from 323 to 873 K were obtained.This study demonstrates that the electrical and thermal transportation of SiGe material can be synergistically tuned by compositing ZrO_(2),illustrating a novel strategy to optimize the TE properties of bulk materials.展开更多
在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以...在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。展开更多
Schimmel腐蚀液腐蚀结合高倍光学显微镜观察发现 ,不同尺寸的掩膜窗内生长的 Si Ge外延层中的位错密度在整个外延层中从 Si Ge/Si界面到 Si Ge外延层表面由少到多 ,再由多到少明显地分成 3个区 .无掩膜窗限制的大面积区内的 Si Ge层则...Schimmel腐蚀液腐蚀结合高倍光学显微镜观察发现 ,不同尺寸的掩膜窗内生长的 Si Ge外延层中的位错密度在整个外延层中从 Si Ge/Si界面到 Si Ge外延层表面由少到多 ,再由多到少明显地分成 3个区 .无掩膜窗限制的大面积区内的 Si Ge层则只呈现 2个区 .掩膜材料与掩膜窗尺寸不同 ,这 3个区的位错密度也不同 .掩膜形成过程中产生的应力对衬底晶格的影响 ,以及掩膜边界对衬底与外延层的影响是造成这种不同的根本原因 .展开更多
Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and pr...Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage. In the light of these principles,a SiGe PMOSFET is designed and fabricated successfully. Measurement indicates that the SiGe PMOSFET's (L=2μm) transconductance is 45 mS/mm (300K) and 92mS/mm (77K), while that is 33 mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.展开更多
基金financially supported by the National Key Research and Development Program of China(Nos.2022YFE0119100 and 2017YFE0198000)the National Natural Science Foundation of China(Nos.U21A2054,52273285,52061009 and 52262032)Guangxi Science and Technology Planning Project(No.AD21220056)。
文摘SiGe-based thermoelectric(TE)materials have gained increasing interests due to their low maintenance costs,environmental friendliness and long lifespan.However,the intrinsically high thermal conductivity of Si-based materials also results in poor TE properties.In this investigation,a zirconia(ZrO_(2))composite strategy was applied to an n-type SiGe alloy,tremendously elevating its TE performance.After mechanical alloying and spark plasma sintering(SPS)processes,the ZrO_(2)induced the formation of nanopores in the SiGe matrix via phosphorus adsorption.Moreover,such increase in porosity enhanced the phonon scattering and dramatically suppressed lattice thermal conductivity,from 2.83 to 1.59 W·m^(-1)·K^(-1)at 873 K.Additionally,reduced phosphorus doping led to an increase in Seebeck coefficients and a relatively minor decrease in electrical conductivity,The power factor didn't deteriorate significantly,either,as its maximum of~3.43 mW·m^(-1-)K^(-2)was achieved at 873 K with(Si_(0.8)Ge_(0.2))_(0.097)P_(0.03)(ZrO_(2))_(0.003).In short,a peak figure of merit(ZT)of~1.27 at 873 K and an average ZT~0.7 from 323 to 873 K were obtained.This study demonstrates that the electrical and thermal transportation of SiGe material can be synergistically tuned by compositing ZrO_(2),illustrating a novel strategy to optimize the TE properties of bulk materials.
文摘在 SOI(Silicon on Insulator)结构硅膜上面生长一层 Si Ge合金 ,采用类似 SOICMOS工艺制作成具有Si Ge沟道的 SOICMOS集成电路。该电路不仅具有 SOICMOS电路的优点 ,而且因为 Si Ge中的载流子迁移率明显高于 Si中载流子的迁移率 ,所以提高了电路的速度和驱动能力。另外由于两种极性的 SOI MOSFET都采用 Si Ge沟道 ,就避免了只有 SOIPMOSFET采用 Si Ge沟道带来的选择性生长 Si Ge层的麻烦。采用二维工艺模拟得到了器件的结构 ,并以此结构参数进行了器件模拟。模拟结果表明 ,N沟和 P沟两种 MOSFET的驱动电流都有所增加 。
文摘Schimmel腐蚀液腐蚀结合高倍光学显微镜观察发现 ,不同尺寸的掩膜窗内生长的 Si Ge外延层中的位错密度在整个外延层中从 Si Ge/Si界面到 Si Ge外延层表面由少到多 ,再由多到少明显地分成 3个区 .无掩膜窗限制的大面积区内的 Si Ge层则只呈现 2个区 .掩膜材料与掩膜窗尺寸不同 ,这 3个区的位错密度也不同 .掩膜形成过程中产生的应力对衬底晶格的影响 ,以及掩膜边界对衬底与外延层的影响是造成这种不同的根本原因 .
基金Supported by National Key Laboratory Fund (99Js09 5.1)
文摘Based on theoretical analysis and computer-aided simulation, optimized design principles for Si/SiGe PMOSFET are given in this paper, which include choice of gate materials,determination of germanium percentage and profile in SiGe channel, optimization of thickness of dioxide and silicon cap layer, and adjustment of threshold voltage. In the light of these principles,a SiGe PMOSFET is designed and fabricated successfully. Measurement indicates that the SiGe PMOSFET's (L=2μm) transconductance is 45 mS/mm (300K) and 92mS/mm (77K), while that is 33 mS/mm (300K) and 39mS/mm (77K) in Si PMOSFET with the same structure.
