A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9...A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.展开更多
A VDMOS integrated in a 170V scan-driver chip of a plasma display panel （PDP） is described,which is based on epitaxial bipolar-CMOS-DMOS （BCD） technology. Some key considerations and parameters of the design are d...A VDMOS integrated in a 170V scan-driver chip of a plasma display panel （PDP） is described,which is based on epitaxial bipolar-CMOS-DMOS （BCD） technology. Some key considerations and parameters of the design are discussed. The thickness of epitaxial layer is 17μm, the area of a single VDMOS structure cell is 324μm^2, and only 18 photoetching steps are needed in the development process. It is also compatible with standard CMOS, bipo- lar,and p-LDMOS devices. The breakdown voltage of VDMOS in the process control module （PCM） is more than 200V. Five kinds of VDMOS modules are integrated in 64 channel PDP scan-driver IC, and on-line system verifica- tion is done on a LG-model-42v6 PDP.展开更多
为提高0.35μm 30-0-50 V BCD(bipolar-CMOS-DMOS)工艺下50 V HVPMOS的电学性能,在不改变工艺流程的基础上,仅通过微调器件结构尺寸来实现电学性能的优化.采用Silvaco公司的工艺与器件模拟软件,仿真分析了沟道长度、overlap尺寸、场氧...为提高0.35μm 30-0-50 V BCD(bipolar-CMOS-DMOS)工艺下50 V HVPMOS的电学性能,在不改变工艺流程的基础上,仅通过微调器件结构尺寸来实现电学性能的优化.采用Silvaco公司的工艺与器件模拟软件,仿真分析了沟道长度、overlap尺寸、场氧化层长度及场极板长度对50 V HVPMOS器件电学性能的影响.根据仿真结果确定了优化后的结构尺寸,并结合流片测试结果验证了优化方案的可行性.测试结果表明,优化后50 V HVPMOS的开启电压降低到了-0.98 V,击穿电压提高到了-68 V,特征导通电阻降低了13.5%,饱和电流提高了13.1%,器件的安全工作范围增大,饱和区更加平滑,无明显kink效应.展开更多
研究表明,0.18μm BCD工艺中SAB膜的厚度对Logic EE IP的数据保持力特性有重大影响。SAB膜越厚,Logic EE IP的数据保持力特性越好;如果SAB膜厚度小于一定尺寸,那么Logic EE IP的数据保持力将会失效。因此适当的SAB膜厚度对保证Logic EE...研究表明,0.18μm BCD工艺中SAB膜的厚度对Logic EE IP的数据保持力特性有重大影响。SAB膜越厚,Logic EE IP的数据保持力特性越好;如果SAB膜厚度小于一定尺寸,那么Logic EE IP的数据保持力将会失效。因此适当的SAB膜厚度对保证Logic EE IP的数据保持力通过合格性测试非常重要。主要研究在标准工艺条件下,通过3种SAB膜厚(标准厚度55 nm、80 nm和100 nm)、老衬底(标准厚度55 nm)、新衬底延长清洗时间(标准厚度55 nm)以及新衬底新生长材料的SAB膜(标准厚度55 nm)等试验,最终确定了在华虹宏力0.18μm BCD工艺平台上,当SAB膜厚度为100 nm时,Logic EE IP核的数据保持力通过了JEDEC标准的合格性测试。展开更多
文摘A high voltage BCD process using thin epitaxial technology is developed for high voltage applications. Compared to conventional thick expitaxial technology, the thickness of the n-type epitaxial layer is reduced to 9μm,and the diffusion processing time needed for forming junction isolation diffusions is substantially reduced. The isolation diffusions have a smaller lateral extent and occupy less chip area. High voltage double RESURF LD- MOS with a breakdown voltage of up to 900V,as well as low voltage CMOS and BJT,are achieved using this high voltage BCD compatible process. An experimental high voltage half bridge gate drive IC using a coupled level shift structure is also successfully implemented, and the high side floating offset voltage in the half bridge drive IC is 880V. The major features of this process for high voltage applications are also clearly demonstrated.
文摘A VDMOS integrated in a 170V scan-driver chip of a plasma display panel （PDP） is described,which is based on epitaxial bipolar-CMOS-DMOS （BCD） technology. Some key considerations and parameters of the design are discussed. The thickness of epitaxial layer is 17μm, the area of a single VDMOS structure cell is 324μm^2, and only 18 photoetching steps are needed in the development process. It is also compatible with standard CMOS, bipo- lar,and p-LDMOS devices. The breakdown voltage of VDMOS in the process control module （PCM） is more than 200V. Five kinds of VDMOS modules are integrated in 64 channel PDP scan-driver IC, and on-line system verifica- tion is done on a LG-model-42v6 PDP.
文摘为提高0.35μm 30-0-50 V BCD(bipolar-CMOS-DMOS)工艺下50 V HVPMOS的电学性能,在不改变工艺流程的基础上,仅通过微调器件结构尺寸来实现电学性能的优化.采用Silvaco公司的工艺与器件模拟软件,仿真分析了沟道长度、overlap尺寸、场氧化层长度及场极板长度对50 V HVPMOS器件电学性能的影响.根据仿真结果确定了优化后的结构尺寸,并结合流片测试结果验证了优化方案的可行性.测试结果表明,优化后50 V HVPMOS的开启电压降低到了-0.98 V,击穿电压提高到了-68 V,特征导通电阻降低了13.5%,饱和电流提高了13.1%,器件的安全工作范围增大,饱和区更加平滑,无明显kink效应.
文摘研究表明,0.18μm BCD工艺中SAB膜的厚度对Logic EE IP的数据保持力特性有重大影响。SAB膜越厚,Logic EE IP的数据保持力特性越好;如果SAB膜厚度小于一定尺寸,那么Logic EE IP的数据保持力将会失效。因此适当的SAB膜厚度对保证Logic EE IP的数据保持力通过合格性测试非常重要。主要研究在标准工艺条件下,通过3种SAB膜厚(标准厚度55 nm、80 nm和100 nm)、老衬底(标准厚度55 nm)、新衬底延长清洗时间(标准厚度55 nm)以及新衬底新生长材料的SAB膜(标准厚度55 nm)等试验,最终确定了在华虹宏力0.18μm BCD工艺平台上,当SAB膜厚度为100 nm时,Logic EE IP核的数据保持力通过了JEDEC标准的合格性测试。
