This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it f...This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.展开更多
文摘This paper describes a built-in self-test (BIST) hardware overheadminimization technique used during a BIST synthesis process. The technique inserts a minimal amountof BIST resources into a digital system to make it fully testable. The BIST resource insertion isguided by the results of symbolic testability analysis. It takes into consideration both BISTregister cost and wiring overhead in order to obtain the minimal area designs. A Simulated Annealingalgorithm is used to solve the overhead minimization problem. Experiments show that consideringwiring area during BIST synthesis results in smaller final designs as compared to the cases when thewiring impact is ignored.
