Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.

A Back-Gated Ferroelectric Field-Effect Transistor with an Al-Doped Zinc Oxide Channel

We report a back-gated metal-oxide-ferroelectric-metal （MOFM） field-effect transistor （FET） with lead zirconate titanate （PZT） material, in which an Al doped zinc oxide （AZO） channel layer with an optimized doping concentration of 1% is applied to reduce the channel resistance of the channel layer, thus guaranteeing a large enough load capacity of the transistor. The hysteresis loops of the Pt/PZT/AZO/Ti/Pt capacitor are measured and compared with a Pt/PZT/Pt capacitor, indicating that the remnant polarization is almost 40 μC/cm^2 and the polarization is saturated at 20 V. The measured capacitance-voltage properties are analyzed as a result of the electron depletion and accumulation switching operation conducted by the modulation of PZT on AZO channel resistance caused by the switchable remnant polarization of PZT. The switching properties of the AZO channel layer are also proved by the current-voltage transfer curves measured in the back-gated MOFM ferroelectric FET, which also show a drain current switching ratio up to about 100 times.

Flexible Graphene Devices with an Embedded Back-Gate

We show the fabrication of flexible graphene devices with an embedded backgate. The resistance of these devices can be tuned by changing the strain through the bending of the substrate. These devices can be useful for applications requiring a flexible graphene-based field effect transistor in where the graphene channel is not covered (such as biological or chemical sensors and photo-detectors).

Impact of back-gate bias on the hysteresis effect in partially depleted SOI MOSFETs

The hysteresis effect in the output characteristics,originating from the floating body effect,has been measured in partially depleted（PD） silicon-on-insulator（SOI） MOSFETs at different back-gate biases.I D hysteresis has been developed to clarify the hysteresis characteristics.The fabricated devices show the positive and negative peaks in the I D hysteresis.The experimental results show that the I D hysteresis is sensitive to the back gate bias in 0.13-渭m PD SOI MOSFETs and does not vary monotonously with the back-gate bias.Based on the steady-state Shockley-Read-Hall（SRH） recombination theory,we have successfully interpreted the impact of the back-gate bias on the hysteresis effect in PD SOI MOSFETs.

Back-Gate Effect of SOI LDMOSFETs

0.5μm-gate-length lateral double-diffused metal-oxide-semiconductor field-effect transistors （LDMOSFETs） with low barrier body contact （LBBC） and body tied to the source （BTS） were fabricated on silicon-on-insulator （SOI） substrates. The back-gate effects on front-channel subthreshold characteristics, on-resistance, and off-state breakdown characteristics of these devices are studied in detail. The LDMOSFETs with the LBBC structure show less back-gate effect than those with the BTS structure due to better control of the floating body effect and suppression of the parasitic backchannel leakage current. A model for the SOl LDMOSFETs has been given,including the front- and back-channel conductions as well as the bias-dependent series resistance.

Highly sensitive and stable β-Ga_(2)O_(3) DUV phototransistor with local back-gate structure and its neuromorphic application

Deep ultraviolet(DUV)phototransistors are key integral of optoelectronics bearing a wide spectrum of applications in flame sensor,military detector,oil spill detection,biological sensor,and artificial intelligence fields.In order to further improve the responsivity of UV photodetectors based onβ-Ga_(2)O_(3),in present work,high-performanceβ-Ga_(2)O_(3) phototransistors with local back-gate structure were experimentally demonstrated.The phototransistor shows excellent DUV photoelectrical performance with a high responsivity of 1.01×107 A/W,a high external quantum efficiency of 5.02×109%,a sensitive detectivity of 2.98×1015 Jones,and a fast rise time of 0.2 s under 250 nm illumination.Besides,first-principles calculations reveal the decent stability ofβGa_(2)O_(3) nanosheet against oxidation and humidity without significant performance degradations.Additionally,the hexagonal boron nitride(h-BN)/β-Ga_(2)O_(3) phototransistor can behave as a photonic synapse with ultralow power consumption of~9.6 fJ per spike,which shows its potential for neuromorphic computing tasks such as facial recognition.Thisβ-Ga_(2)O_(3) phototransistor will provide a perspective for the next generation optoelectrical systems.

Stability analysis of a back-gate graphene transistor in air environment

The stability of a graphene field effect transistor（GFET） is important to its performance optimization, and study of hysteresis behavior can propose useful suggestions for GFET fabrication and optimization.In this work,a back-gate GFET has been fabricated and characterized,which is compatible with the CMOS process.The stability of a GFET in air has been studied and it is found that a GFET＇s electrical performance dramatically changes when exposed to air.The hysteresis characteristic of a GFET depending on time has been observed and analyzed systematically.Hysteresis behavior is reversed at room temperature with the Dirac point positive shifted when the GFET is exposed to air after annealing.

Influence of back-gate stress on the back-gate threshold voltage of a LOCOS-isolated SOI MOSFET

The performance of a LOCOS-isolated SOI MOSFET heavily depends on its back-gate characteristic, which can be affected by back-gate stress.A large voltage stress was applied to the back gate of SOI devices for at least 30 s at room temperature,which could effectively modify the back-gate threshold voltage of these devices. This modification is stable and time invariant.In order to improve the back-gate threshold voltage,positive substrate bias was applied to NMOS devices and negative substrate bias was applied to PMOS devices.These results suggest that there is a leakage path between source and drain along the silicon island edge,and the application of large backgate bias with the source,drain and gate grounded can strongly affect this leakage path.So we draw the conclusion that the back-gate threshold voltage,which is directly related to the leakage current,can be influenced by back-gate stress.

具有高K背栅的无电压回跳RC-IGBT静态特性研究

针对传统RC-IGBT导通压降大、击穿电压低等问题,提出一种具有高介电常数(高K)背栅的RC-IGBT器件结构,其特点是位于底部集电极的背栅介质采用高介电常数材料。高K介质增大了正向导通时背栅周围的空穴浓度,不仅消除了电压回跳,还降低了导通压降。仿真结果表明:在高正向导通电流密度下(I_(CE)=925 A/cm^(2)),高K背栅RC-IGBT的导通压降为1.71 V,相比传统RC-IGBT降低了19.34%,相比氧化层背栅RC-IGBT降低了13.20%;另一方面,在阻断状态下,高K介质增强了背栅周围的电子积累,增大了击穿电压。高K背栅RC-IGBT的击穿电压为1 312 V,相较于氧化层背栅RC-IGBT提高了44.18%。此外,高K背栅RC-IGBT的反向导通压降相比传统RC-IGBT降低了43.43%,相比氧化层背栅RC-IGBT降低了13.85%。将所提出的高K背栅的RC-IGBT应用于高压、大功率的电子电力系统,可提高系统的可靠性并降低损耗。

WS_(2)场效应晶体管的表面电子掺杂

二硫化钨(WS_(2))属于过渡金属硫族化合物(TMDs)材料,具有较宽的可调带隙(1.3~2.1 e V),缺陷密度相对较低,且有超高的表面积比,可通过外界掺杂或相变处理来改善载流子传输性能,在低功耗场效应晶体管和超灵敏光电探测器等领域有广阔的应用前景。采用微机械剥离的方法将多层WS_(2)薄膜转移到氧化铪(HfO2)介质层上,制备出具有高栅控、低功耗的WS_(2)背栅场效应晶体管,通过注入三乙胺(TEA)实现WS_(2)薄膜的表面电子掺杂。实验结果表明,修饰后的多层WS_(2)薄膜的面内振动模式有轻微位移,拉曼特征峰强度变弱,证明三乙胺溶液能有效增加WS_(2)薄膜内的电子浓度;薄膜与金属电极之间的欧姆接触良好,器件的电子迁移率由10.87 cm^(2)·V^(-1)·s^(-1)提升到24.89 cm^(2)·V^(-1)·s^(-1),室温下的电流开关比保持在106,亚阈值摆幅为190.11 m V/dec。结合理论分析TEA对WS_(2)原子薄层的掺杂机理,TEA通过表面电荷转移的方式来增加WS_(2)半导体内的电子浓度,完成WS_(2)背栅场效应晶体管的n型掺杂。器件较高的电流开关比及电子迁移率的提升证明了TEA的表面修饰能有效调控多层WS_(2)晶体管器件的电子传输特性。

基于GRU-BP算法的高精度动态物流称重系统

针对动态物流秤测量精度对载重、采样频率、带速较为敏感的问题,提出了一种高精度动态物流称重系统。首先,采用三因素五水平正交试验法,结合皮尔逊相关性检验原则,使用低通巴特沃斯与卡尔曼滤波器对传感器压力信号进行了滤波降噪处理,并将加速度信号作为模型输入信号,进行了特征补偿;然后,基于深度学习算法,提出了一种改进的门控循环单元模型,在该模型采样区间内将压力与振动改写为时序化信号,并将其共同输入门控循环单元(GRU)模型;最后,对GRU模型进行了改进,对其结构输出了层堆叠误差反向传播神经网络(BP),有效加强了模型的非线性映射能力。研究结果表明:在各类传动速度及测试货物下,该模型的最大测量误差相对于同类型深度学习模型长短期记忆(LSTM)神经网络、循环神经网络(RNN)时序模型及传统数值平均模型的误差,依次降低了16.14%、27.14%、76%,可用于各类称重系统。

基于EMD-BPNN的逆变器IGBT开路故障诊断方法

绝缘栅双极性晶体管(Insulated gate bipolar transistor,IGBT)作为逆变器的主要组成部分,其工作的稳定性与可靠性对逆变器的正常工作有着重要的影响。针对三相电机牵引逆变器IGBT常见的单管和双管开路故障,提出一种基于经验模态分解(Empirical mode decomposition,EMD)和误差反向传播神经网络(Back propagation neural network,BPNN)相结合的故障诊断方法。首先分析逆变器IGBT单管和双管开路故障的波形特征,采用EMD方法对逆变器输出的三相电流进行分解;在此基础上构造故障特征向量,采用BPNN对特征向量进行训练并实现故障诊断;其次针对EMD方法存在的“模态混叠”问题,采用互补集合经验模态分解(Complementary ensemble empirical mode decomposition,CEEMD)对诊断方法进行了优化;最后在小型试验平台上进行了试验,试验结果表明,基于CEEMD-BPNN的故障诊断方法能够有效诊断出故障功率管。

基于无线静态应变测量技术的人字闸门背拉杆预应力调整研究

为研究无线静态应变测量技术在大型船闸金属结构件应变检测中的应用,利用无线静态应变测量技术开展工程实践,探讨了无线静态应变测量技术在船闸人字闸门背拉杆预应力调整应用中的可行性,并在2022年实施的某大型船闸计划性停航检修中,对下游两扇人字闸门背拉杆进行了改造及预应力调整。结果表明:经过通航之后运行检查,闸门使用效果良好。该技术能够提高检测的精度和传输可靠性,具有高效、便捷的优点,研究成果可为船闸人字闸门背拉杆静态应变测量提供新的解决方案,同时能够为人字闸门的检修提供可靠的数据支持。

鱼梁船闸检修人字门背拉杆调整工艺及设备应用

文章介绍鱼梁船闸检修人字门背拉杆调整的必要性和调整工艺、背拉杆应力检测方法与设备、调整工装及加载系统,并在实际工程中应用,为同行业船闸检修人员提供经验,为编制更科学、高效的背拉杆调整工艺提供有效参考。

背接触电池的低温主栅工艺分析

阐述主栅材料、电极结构和烘干工艺方面对背接触电池的影响,通过优化相关参数实现背接触电池的高转换效率,从而获得成本较低、生产节奏较快、效率更优的主栅工艺,促进生产发展。

28nm高K金属栅技术平台光阻回刻工艺中提高刻蚀工艺稳定性的方法研究

阐述在28nm高K金属栅(28HKMG)技术平台中解决NMOS/PMOS区域栅极阻挡层高度差的主要方案,是在金属栅极制造工艺前插入光阻回刻系列工艺流程,使NMOS区域与PMOS区域的栅极高度获得一致。但该方案在实际量产中的主要难点是第二道回刻工艺(Etch Back2,即EB2)不稳定,腔体的刻蚀速率与面内分布随着作业时间的增加会出现明显的趋势变化,导致产品端用于表征刻蚀结果的量测参数“牛角高度”(Spacer1二氧化硅保护层高度与栅极高度之间的高度差)在片内具有较高波动性,易造成缺陷,无法安全生产。为此,详细探讨28HKMG平台EB2刻蚀工艺不稳定的原因,并针对实际量产过程中发生的异常,给出切实可行的解决方案,有利于维护腔体微环境稳定,提高产品质量。

光阻回刻工艺缺陷与改善方法研究

阐述在金属栅极(例如AL)半导体芯片制造工艺中通常需要引入一段特有流程用来去除多晶硅(Poly)并进行金属再填充。光阻回刻工艺作为该流程中的关键步骤,主要目的是去除Poly顶端的硬质掩膜,便于后道工艺对Poly进行刻蚀。因为NMOS和PMOS的硬质掩膜存在高度差异,以及光阻在不同图形密度区域厚度不同,导致工艺窗口紧张,实际生产维护困难,容易出现包括多晶硅残留在内的多种缺陷,严重影响产品最终良率。为此,通过对缺陷进行分类,探究形成机理,提出对应在线监控方式,能够降低缺陷发生率,并尝试对工艺条件进行优化,提升整体工艺窗口。

D类音频功率放大器中的死区控制电路设计

设计了一种用于D类音频功率放大器中产生死区时间的互锁电路,通过对功率管的输出状态进行检测,使得在每种状态下只有一个功率管导通,有效地防止了上下功率管的同时导通,从而减小了功率级的损耗,提高了放大器的效率.针对该互锁电路提出了一种死区时间设计方法,使得在有效抑制功率管导通的同时引入最小的失真,同时对引入死区时间所产生的影响做了详细分析.仿真结果表明:该互锁电路在输出信号的上升沿产生的死区时间为13.6 ns,在输出信号的下降沿产生的死区时间为15.5 ns.

氧化锌纳米线晶体管的电学特性研究

成功制作了氧化锌纳米线沟道场效应晶体管器件,所制作器件的电学性能通过I-V测试进行了分析。使用了水浴法生长了单晶性完整的氧化锌纳米线,该纳米线被用作背栅场效应晶体管的沟道,采用光刻方式制备的器件具有良好的直流特性,进行退火后进一步改善器件的源漏接触,提高器件性能,最终制备成功的场效应晶体管显示出p型MOS的特性,其开关态电流比达到105。在Vds=2.5 V时,跨导峰值为0.4μS,栅氧电容约为0.9 fF,器件夹断电压Vth为0.6 V,沟道迁移率约为87.1 cm2/V.s,计算得到氧化锌纳米线载流子浓度ne=6.8×108 cm-3。在Vgs=0 V时,器件沟道电阻率为100Ω.cm。

大和水闸过闸流量分析

着重考虑了闸上下游行近段的河道形态对水流结构的影响,即当行近水流流向偏离水闸纵向轴线时,回流、过闸水流的不对称等将降低水闸的过闸能力.根据观澜河大和水闸的实验结果,分析了回流、过闸水流的不对称等影响闸孔过流能力的规律.在此基础上,根据实验结果,给出了修正的计算公式,检验结果表明所建立的修正公式较适用大和水闸过闸流量的计算.