Novel p-Channel Selected n-Channel Divided Bit-Line NOR Flash Memory Using Source Induced Band-to-Band Hot Electron Injection Programming

A novel p-channel selected n-channel divided bit-line NOR(PNOR) flash memory,which features low programming current,low power,high access current,and slight bit-line disturbance,is proposed.By using the source induced band-to-band hot electron injection (SIBE) to perform programming and dividing the bit-line to the sub-bit-lines,the programming current and power can be reduced to 3.5μA and 16.5μW with the sub-bit-line width equaling to 128,and a read current of 60μA is obtained.Furthermore,the bit-line disturbance is also significantly alleviated.

Hetero-gate-dielectric double gate junctionless transistor(HGJLT)with reduced band-to-band tunnelling effects in subthreshold regime

We propose a hetero-gate-dielectric double gate junctionless transistor （HGJLT）, taking high-k gate insulator at source side and low-k gate insulator at drain side, which reduces the effects ＆band-to-band tunnelling （BTBT） in the sub-threshold region. A junctionless transistor （JLT） is turned off by the depletion of carriers in the highly doped thin channel （device layer） which results in a significant band overlap between the valence band of the channel region and the conduction band of the drain region, due to off-state drain bias, that triggers electrons to tunnel from the valence band of the channel region to the conduction band of the drain region leaving behind holes in the channel.These effects of band-to-band tunnelling increase the sub-threshold leakage current, and the accumulation of holes in the channel forms a parasitic bipolar junction transistor （n-p-n BJT for channel JLT） in the lateral direction by the source （emitter）, channel （base） and drain （collector） regions in JLT structure in off-state. The proposed HGJLT reduces the subthreshold leakage current and suppresses the parasitic BJT action in off-state by reducing the band-to-band tunnelling probability.

Comparison of band-to-band tunneling models in Si and Si–Ge junctions

We compared several different band-to-band tunneling （BTBT） models with both Sentaurus and the two-dimensional full-band Monte Carlo simulator in Si homo-junctions and Si-Ge hetero-junctions. It was shown that in Si homo-junctions, different models could achieve similar results. However, in the Si-Ge hetero-junctions, there were significant differences among these models at high reverse biases （over 2 V）. Compared to the nonlocal model, the local models in Sentaurus underrated the BTBT rate distinctly, and the Monte Carlo method was shown to give a better approximation. Additionally, it was found that in the Si region near the interface of the Si-Ge hetero-junctions, the direct tunneling rates increased largely due to the interaction of the band structures of Si and Ge.

High on-state current p-type tunnel effect transistor based on doping modulation

To solve the problem of the low on-state current in p-type tunnel field-effect transistors(p-TFETs),this paper analyzes the mechanism of adjusting the tunneling current of a TFET device determined by studying the influence of the peak position of ion implantation on the potential of the p-TFET device surface and the width of the tunneling barrier.Doping-regulated silicon-based high on-state p-TFET devices are designed and fabricated,and the test results show that the on-state current of the fabricated devices can be increased by about two orders of magnitude compared with the current of other devices with the same structure.This method provides a new idea for the realization of high on-state current TFET devices.

Investigation of the characteristics of GIDL current in 90nm CMOS technology

A specially designed experiment is performed for investigating gate-induced drain leakage （GIDL） current in 90nm CMOS technology using lightly-doped drain （LDD） NMOSFET. This paper shows that the drain bias VD has a strong effect on GIDL current as compared with the gate bias VG at the same drain-gate voltage VDG. It is found that the difference between ID in the off-state ID - VG characteristics and the corresponding one in the off-state ID - VD characteristics, which is defined as IDIFF, versus VDG shows a peak. The difference between the influences of VD and VG on GIDL current is shown quantitatively by IDIFF, especially in 90nm scale. The difference is due to different hole tunnellings, Furthermore, the maximum IDIFF（IDIFF,MAX） varies linearly with VDG in logarithmic coordiuates and also VDG at IDIFF,MAX with VF which is the characteristic voltage of IDIFF, The relations are studied and some related expressions are given.

HIGH-ACCURACY BAND TO BAND REGISTRATION METHOD FOR MULTI-SPECTRAL IMAGES OF HJ-1A/B

Band-to-band registration accuracy is an important parameter of multispectral data. A novel band-to-band registration approach with high precision is proposed for the multi-spectral images of HJ-1A/B. Firstly, the main causes resulted in misregistration are analyzed, and a high-order polynomial model is proposed. Secondly, a phase fringe filtering technique is employed to Phase Correlation Method based on Singular Value Decomposition (SVD-PCM) for reducing the noise in phase difference matrix. Then, experiments are carried out to build nonlinear registration models, and images of green band and red band are aligned to blue band with an accuracy of 0.1 pixels, while near infrared band with an accuracy of 0.2 pixels.

Total ionizing dose induced single transistor latchup in 130-nm PDSOI input/output NMOSFETs

Total ionizing dose induced single transistor latchup effects for 130 nm partially depleted silicon-on-insulator （PDSOI） NMOSFETs with the bodies floating were studied in this work. The latchup phenomenon strongly correlates with the bias configuration during irradiation. It is found that the high body doping concentration can make the devices less sensitive to the single transistor latchup effect, and the onset drain voltage at which latchup occurs can degrade as the total dose level rises. The mechanism of band-to-band tunneling （BBT） has been discussed. Two-dimensional simulations were conducted to evaluate the BBT effect. It is demonstrated that BBT combined with the positive trapped charge in the buried oxide （BOX） contributes a lot to the latchup effect.

Two-dimensional threshold voltage model of a nanoscale silicon-on-insulator tunneling field-effect transistor

The tunneling field-effect transistor（TFET） is a potential candidate for the post-CMOS era.In this paper,a threshold voltage model is developed for this new kind of device.First,two-dimensional（2D） models are used to describe the distributions of potential and electric field in the channel and two depletion regions.Then based on the physical definition of threshold voltage for the nanoscale TFET,the threshold voltage model is developed.The accuracy of the proposed model is verified by comparing the calculated results with the 2D device simulation data.It has been demonstrated that the effects of varying the device parameters can easily be investigated using the model presented in this paper.This threshold voltage model provides a valuable reference to TFET device design,simulation,and fabrication.

Impact of low/high-κ spacer-source overlap on characteristics of tunnel dielectric based tunnel field-effect transistor

The effects of low-κ and high-κ spacer were investigated on the novel tunnel dielectric based tunnel field-effect transistor(TD-FET) mainly based upon ultra-thin dielectric direct tunneling mechanism. Drive currents consist of direct tunneling current and band-to-band tunneling(BTBT) current. Meanwhile, tunneling position of the TD-FET differs from conventional tunnel-FET in which the electron and hole tunneling occur at intermediate rather than surface in channel(or source-channel junction under gate dielectric). The 2-D nature of TD-FET current flow is also discussed that the on-current is degraded with an increase in the spacer width. BTBT current will not begin to play part in tunneling current until gate voltage is 0.2 V. We clearly identify the influence of the tunneling dielectric layer and spacer electrostatic field on the device characteristics by numerical simulations. The inserted Si_3N_4 tunnel layer between P+ region and N+ region can significantly shorten the direct and band-to-band tunneling path, so a reduced subthreshold slope(Ss) and a high on-current can be achieved. Above all the ambipolar current is effectively suppressed, thus reducing off-current. TD-FET demonstrates excellent performance for low-power applications.

Characteristic enhancement in tunnel field-effect transistors via introduction of vertical graded source

A novel vertical graded source tunnel field-effect transistor(VGS-TFET)is proposed to improve device performance.By introducing a source with linearly graded component,the on-state current increases by more than two decades higher than that of the conventional GaAs TFETs without sacrificing the subthreshold swing(SS)due to the improved band-to-band tunneling efficiency.Compared with the conventional TFETs,much larger drive current range can be achieved by the proposed VGS-TFET with SS below the thermionic limitation of 60 mV/dec.Furthermore,the minimum SS about 20 mV/dec indicates its promising potential for further ultralow power applications.

Temperature effect on hetero structure junctionless tunnel FET

For the first time, we investigate the temperature effect on AIGaAs/Si based hetero-structure junction- less double gate tunnel field effect transistor. Since junctionless tunnel FET is an alternative substitute device for ultra scaled deep-submicron CMOS technology, having very good device characteristics such as an improved sub- threshold slope （〈 60 mV/decade at 300 K） and very small static leakage currents. The improved subthreshold slope and static leakage current confirms that it will be helpful for the development of future low power switching circuits. The 2-D computer based simulation results show that OFF-state leakage current is almost temperature independent for the proposed device structure.

A simulation-based proposed high-k heterostructure AlGaAs/Si junctionless n-type tunnel FET

We propose a heterostructure junctionless tunnel field effect transistor （HJL-TFET） using AIGaAs/Si. In the proposed HJL-TFET, low band gap silicon is used in the source side and higher band gap AlGaAs in the drain side. The whole AlGaAs/Si region is heavily doped n-type. The proposed HJL-TFET uses two isolated gates （named gate, gatel ） with two different work functions （gate = 4.2 eV, gatel = 5.2 eV respectively）. The 2-D nature of HJL-TFET current flow is studied. The proposed structure is simulated in Silvaco with different gate dielectric materials. This structure exhibits a high on current in the range of 1.4 × 10^-6 A/μm, the off current remains as low as 9.1 × 10^-14 A/μm. So /ON/OFF ratio of 10^8 is achieved. Point subthreshold swing has also been reduced to a value of 41 mV/decade for TiO2 gate material.

A novel sub 20 nm single gate tunnel field effect transistor with intrinsic channel for ultra low power applications

We propose a nanoscale single gate ultra thin body intrinsic channel tunnel field effect transistor using the charge plasma concept for ultra low power applications. The characteristics of TFETs （having low leakage） are improved by junctionless TFETs through blending advantages of Junctionless FETs （with high on current）. We further improved the characteristics, simultaneously simplifying the structure at a very low power rating using an InAs channel. We found that the proposed device structure has reduced short channel effects and parasitics and provides high speed operation even at a very low supply voltage with low leakage. Simulations resulted in Iovv of - 9 × 10-16A/um, IoN of ,-20uA/um, ION/IoFF of--2× 1010, threshold voltage of 0.057 V, subthreshold slope of 7 mV/dec and DIBL of 86 mV/V for PolyGate/HfO2/InAs TFET at a temperature of 300 K, gate length of 20 nm, oxide thickness of 2 nm, film thickness of 10 nm, low-k spacer thickness of 10 nm and VDD of 0.2 V.

Broadband electroluminescence from reverse breakdown in individual suspended carbon nanotube pn-junctions

There are various mechanisms of light emission in carbon nanotubes (CNTs), which give rise to a wide range of spectral emission characteristics that provide important information regarding the underlying physical processes that lead to photon emission. Here, we report spectra obtained from individual suspended CNT dual-gate field effect transistor (FET) devices under different gate and bias conditions. By applying opposite voltages to the gate electrodes (i.e., Vg1 = –Vg2), we are able to create a pn-junction within the suspended region of the CNT. Under forward bias conditions, the spectra exhibit a peak corresponding to E11 exciton emission via thermal (i.e., blackbody) emission occurring at electrical powers around 8 μW, which corresponds to a power density of approximately 0.5 MW/cm2. On the other hand, the spectra observed under reverse bias correspond to impact ionization and avalanche emission, which occurs at electrical powers of ~ 10 nW and exhibits a featureless flat spectrum extending from 1,600 nm to shorter wavelengths up to 600 nm. Here, the hot electrons generated by the high electric fields (~ 0.5 MV/cm) are able to produce high energy photons far above the E11 (ground state) energy. It is somewhat surprising that these devices do not exhibit light emission by the annihilation of electrons and holes under forward bias, as in a light emitting diode (LED). Possible reasons for this are discussed, including Auger recombination.

Temperature dependent I_(DS)–V_(GS) characteristics of an N-channel Si tunneling field-effect transistor with a germanium source on Si(110) substrate

We fabricated n-type Si-based TFETs with a Ge source on Si（110） substrate. The temperature dependent IDS-VGS characteristics of a TFET formed on Si（110） are investigated in the temperature range of 210 to 300 K. A study of the temperature dependence of/Leakage indicates that/Leakage is mainly dominated by the Shockley-Read- Hall （SRH） generation-recombination current of the n＋ drain-Si substrate junction, ION increases monotonically with temperature, which is attributed to a reduction of the bandgap at the tunneling junction and an enhancement of band-to-band tunneling rate. The subthreshold swing S for trap assisted tunneling （TAT） current and band-to- band tunneling （BTBT） current shows the different temperature dependence. The subthreshold swing S for the TAT current degrades with temperature, while the S for BTBT current is temperature independent.

Two-dimensional phosphorene/C_3N p-n heterostructure: Effect of contact type on electronic and optical properties

p-n heterostructure(HTS) is a fundamental component for high-performance electronic and optoelectronic device. Vertical stacking through van der Waals(vdW) force is emerging as a feasible technique to construct p-n HTS. Herein, we designed a novel kind of direct-bandgap C_3N monolayer, via adjusting the arrangement of C and N atoms in C_3N hexagonal cell. On the basis of the density functional theory combined with the non-equilibrium Green's function method, we built two-dimensional vdW-contact phosphorene(BP)/C_3N p-n HTS, and analyzed its electronic and optical properties in comparison with the inplanejointed ones. The strong charge transfer between BP and C_3N segments results in a wide bandgap of 0.48 eV for joint-contact type BP/C_3N HTS, whereas the effective interlayer coupling in vdW-contact type leads to an improved light adsorption as compared to the isolated C_3N monolayer. By fabricating dual-gated BP/C_3N HTS field-effect transistors(FETs), the dynamic transport behaviors demonstrated that the band bending under a lower threshold voltage makes band-to-band tunneling possible for vdW-contact type. Our work suggests that vdW-contact type is superior to joint-contact type in constructing p-n HTS for high-performance electronic and optoelectronic devices.

GIDL current degradation in LDD nMOSFET under hot hole stress

The degradation of gate-induced drain leakage （GIDL） current in LDD nMOSFET under hot holes stress is studied in depth based on its parameter IDIFF. IDIFF is the difference of GIDL currents measured under two conditions of drain voltage VD = 1.4 V and gate voltage VG = -1.4 V while FoG is fixed. After the stress GIDL currents decay due to holes trapping in the oxide around the gate-to-drain overlap region. These trapped holes diminish A Ex which is the deference of the lateral electrical field of these two symmetrical measurement conditions in the overlap region so as to make IDIFF lessening. IOIFF extracted from GIDL currents decreases with increasing stress time t. The degradation shifts of IDIFF, MAX （A IDWF, MAX） follows a power law against t： △IDIFF＇ MAX （x t^m, m = 0.3. Hot electron stress is performed to validate the related mechanism.

Nanoscale Ⅲ-Ⅴ on Si-based junctionless tunnel transistor for EHF band applications

A single gate Ⅲ-Ⅴ junctionless tunnel field effect transistor（SG-JLTFET） has been reported which shows excellent dc characteristics at low power supply operation.This device has a thin uniformly n-type doped channel of GaSb i.e.gallium antimonide which is grown epitaxially over silicon substrate.The DC performance parameters such as I（on）,I（on）/I（off）,average and point subthreshold slope as well as device parameters for analog applications viz.transconductance gm,transconductance generation efficiency gm/ID,various capacitances and the unity gain frequency fT are studied using a device simulator.Along with examining its endurance to short channel effects,the performances are also compared with a Silicon Dual Gate Junctionless Tunnel FET（DG-JLTFET）.The DC and small signal analog performance reflects that GaSb SG-JLTFET has immense purview for extreme high-frequency and low-power applications.

Design and simulation of nanoscale double-gate TFET/tunnel CNTFET

A double-gate tunnel field-effect transistor （DG tunnel FET） has been designed and investigated for various channel materials such as silicon （Si）, gallium arsenide （GaAs）, alminium gallium arsenide （A1xGa1-xAs） and CNT using a nano ViDES Device and TCAD SILVACO ATLAS simulator. The proposed devices are com- pared on the basis of inverse subthreshold slope （SS）, ION/IoFF current ratio and leakage current. Using Si as the channel material limits the property to reduce leakage current with scaling of channel, whereas the A1xGa1-xAs based DG tunnel FET provides a better ION/IOFF current ratio （2.51 × 10^6） as compared to other devices keeping the leakage current within permissible limits. The performed silmulation of the CNT based channel in the double-gate tunnel field-effect transistor using the nano ViDES shows better performace for a sub-threshold slope of 29.4 mV/dec as the channel is scaled down. The proposed work shows the potential of the CNT channel based DG tunnel FET as a futuristic device for better switching and high retention time, which makes it suitable for memory based circuits.