An Adaptive-Bandwidth CMOS PLL with Low Jitter and a Wide Tuning Range

This paper presents a novel adaptive-bandwidth charge pump PLL with low jitter and a wide tuning range. With an adaptive bandwidth,the proposed PLL can scale its loop dynamics proportional to the output frequency and maintain optimal performance over its entire output range. In order to improve the jitter performance of the PLL,a matching tech- nique is employed in the charge pump,and a voltage-to-voltage converter is used to achieve a low gain VCO. The experimental chip was fabricated in a 0. 35μm CMOS process. The measured results show that the PLL has perfect jitter performance within its operating range from 200MHz to 1.1GHz.

Bandwidth adaption for kernel particle filter

A novel particle filter bandwidth adaption for kernel particle filter （BAKPF） is proposed. Selection of the kernel bandwidth is a critical issue in kernel density estimation （KDE）. The plug-in method is adopted to get the global fixed bandwidth by optimizing the asymptotic mean integrated squared error （AMISE） firstly. Then, particle-driven bandwidth selection is invoked in the KDE. To get a more effective allocation of the particles, the KDE with adap- tive bandwidth in the BAKPF is used to approximate the posterior probability density function （PDF） by moving particles toward the posterior. A closed-form expression of the true distribution is given. The simulation results show that the proposed BAKPF performs better than the standard particle filter （PF）, unscented particle filter （UPF） and the kernel particle filter （KPF） both in efficiency and estimation precision.

Jitter Reduced Self Biased PLLs—A Systematic Simulation Study

The self biased Phase Locked Loop (PLL) has become a default choice for clock generation in many microprocessors. In today’s scenario, the processor cores are made to operate at rapidly varying combinations of clock frequencies and very low supply voltages. Though the traditional self biased PLL is still being widely used with hardly any modification, it is becoming imperative to take a relook at the design aspects of these PLLs with respect to their jitter performance. This paper presents a systematic simulation study of designing the self biased PLL with the goal of reducing jitter. It further shows that if the self biased PLL is adapted into a dual loop scheme in a systematic manner, a significant jitter improvement can be obtained. Detailed simulations carried out in 0.18 μm CMOS technology indicate a reduction of 56% or more in jitter for the systematically designed dual loop scheme in comparison to the jitter reduced traditional self biased PLL.

Kernel Quantile Estimator with ICI Adaptive Bandwidth Selection Technique

In this article, we consider a class of kernel quantile estimators which is the linear combi- nation of order statistics. This class of kernel quantile estimators can be regarded as an extension of some existing estimators. The exact mean square error expression for this class of estimators will be provided when data are uniformly distributed. The implementation of these estimators depends mostly on the bandwidth selection. We then develop an adaptive method for bandwidth selection based on the intersection confidence intervals （ICI） principle. Monte Carlo studies demonstrate that our proposed approach is comparatively remarkable. We illustrate our method with a real data set.