High-Bandwidth,Low-Power CMOS Transistor Based CAB for Field Programmable Analog Array

This article presents an integrated current mode configurable analog block(CAB)system for field-programmable analog array(FPAA).The proposed architecture is based on the complementary metal-oxide semiconductor(CMOS)transistor level design where MOSFET transistors operating in the saturation region are adopted.The proposed CAB architecture is designed to implement six of thewidely used current mode operations in analog processing systems:addition,subtraction,integration,multiplication,division,and pass operation.The functionality of the proposed CAB is demonstrated through these six operations,where each operation is chosen based on the user’s selection in the CAB interface system.The architecture of the CAB system proposes an optimized way of designing and integrating only three functional cells with the interface circuitry to achieve the six operations.Furthermore,optimized programming and digital tuning circuitry are implemented in the architecture to control and interface with the functional cells.Moreover,these designed programming and tuning circuitries play an essential role in optimizing the performance of the proposed design.Simulation of the proposed CMOS Transistor Based CAB system is carried out using Tanner EDA Tools in 0.35μm standard CMOS technology.The design uses a±1.5 V power supply and results in maximum 3 dB bandwidth of 34.9 MHz and an approximate size of 0.0537 mm2.This demonstrates the advantages of the design over the current state-of-the-art designs presented for comparison in this article.Consequently,the proposed design has a clear aspect of simplicity,low power consumption,and high bandwidth operation,which makes it a suitable candidate for mobile telecommunications applications.

A HW/SW Co-Verification Technique for FPGA Test

Field programmable gate arrays （FPGAs） have wide and extensive applications in many areas. Due to programmable feature of FPGAs, faults of FPGAs can be easily tolerated if fault sites can be located. A hardware/software （HW/SW） co-verification technique for FPGA test is proposed in this paper. Taking advantage of flexibility and observability of software in conjunction with high-speed simulation of hardware, this technique is capable of testing each input/output block （IOB） and configurable logic block （CLB） of FPGA automatically, exhaustively and repeatedly. Fault cells of FPGA can be positioned automatically by the proposed approach. As a result, test efficiency and reliability can be enhanced without manual work.

Novel Test Approach for Interconnect Resources in Field Programmable Gate Arrays

A novel test approach for interconnect resources （IRs） in field programmable gate arrays （FPGA） has been proposed.In the test approach,SBs （switch boxes） of IRs in FPGA has been utilized to test IRs.Furthermore,configurable logic blocks （CLBs） in FPGA have also been employed to enhance driving capability and the position of fault IR can be determined by monitoring the IRs associated SBs.As a result,IRs can be scanned maximally with minimum configuration patterns.In the experiment,an in-house developed FPGA test system based on system-on-chip （SoC） hardware/software verification technology has been applied to test XC4000E family of Xilinx.The experiment results revealed that the IRs in FPGA can be tested by 6 test patterns.

MIXED-GRAINED CMOS FIELD PROGRAMMABLE ANALOG ARRAY FOR SMART SENSORY APPLICATIONS

The drive towards shorter design cycles for analog integrated circuits has given impetus to the development of Field Programmable Analog Arrays(FPAAs),which are the analogue counterparts of Field Programmable Gate Arrays(FPGAs).In this paper,we present a new design methodology which using FPAA as a powerful analog front-end processing platform in the smart sensory microsystem.The proposed FPAA contains 16 homogeneous mixed-grained Configurable Analog Blocks(CABs) which house a variety of processing elements especially the proposed fine-grained Core Configurable Amplifiers(CCAs).The high flexible CABs allow the FPAA operating in both continuous-time and discrete-time approaches suitable to support variety of sensors.To reduce the nonideal parasitic effects and save area,the fat-tree interconnection network is adopted in this FPAA.The functionality of this FPAA is demonstrated through embedding of voltage and capacitive sensor signal readout circuits and a configurable band pass filter.The minimal detectable voltage and capacitor achieves 38 uV and 8.3 aF respectively within 100 Hz sensor bandwidth.The power consumption comparison of CCA in three applications shows that the FPAA has high power efficiency.And the simulation results also show that the FPAA has good tolerance with wide PVT variations.

Design and analysis of a dual mode CMOS field programmable analog array

This paper presents a novel field-programmable analog array （FPAA） architecture featuring a dual mode including discrete-time （DT） and continuous-time （CT） operation modes, along with a highly routable connection boxes （CBs） based interconnection lattice. The dual mode circuit for the FPAA is capable of achieving targeted op- timal performance in different applications. The architecture utilizes routing switches in a CB not only for the signal interconnection purpose but also for control of the electrical charge transfer required in switched-capacitor circuits. This way, the performance of the circuit in either mode shall not be hampered with adding of programmability. The proposed FPAA is designed and implemented in a 0.18 μm standard CMOS process with a 3.3 V supply voltage. The result from post-layout simulation shows that a maximum bandwidth of 265 MHz through the interconnection network is achieved. The measured results from demonstrated examples show that the maximum signal bandwidth of up to 2 MHz in CT mode is obtained with the spurious free dynamic range of 54 dB, while the signal processing precision in DT mode reaches 96.4%.

A new FPGA with 4/5-input LUT and optimized carry chain

A new LUT and carry structure embedded in the configurable logic block of an FPGA is proposed. The LUT is designed to support both 4-input and 5-input structures, which can be configured by users according to their needs without increasing interconnect resources. We also develop a new carry chain structure with an optimized critical path. Finally a newly designed configurable scan-chain is inserted. The circuit is fabricated in 0.13μm 1P8M 1.2/2.5/3.3 V logic CMOS process. The test results show a correct function of 4/5-input LUT and scan- chain, and a speedup in carry performance of nearly 3 times over current architecture in the same technology at the cost of an increase in total area of about 72.5%. Our results also show that the logic utilization of this work is better than that of a Virtex lI/Virtex 4/Virtex 5/Virtex 6/Virtex 7 FPGA when implemented using only 4-LUT and better than that of a Virtex lI/Virtex 4 FPGA when implemented using only 5-LUT.