Voltage-dependent plasticity and image Boolean operations realized in a WOx-based memristive synapse

The development of electronic devices that possess the functionality of biological synapses is a crucial step towards neuromorphic computing.In this work,we present a WOx-based memristive device that can emulate voltage-dependent synaptic plasticity.By adjusting the amplitude of the applied voltage,we were able to reproduce short-term plasticity(STP)and the transition from STP to long-term potentiation.The stimulation with high intensity induced long-term enhancement of conductance without any decay process,thus representing a permanent memory behavior.Moreover,the image Boolean operations(including intersection,subtraction,and union)were also demonstrated in the memristive synapse array based on the above voltage-dependent plasticity.The experimental achievements of this study provide a new insight into the successful mimicry of essential characteristics of synaptic behaviors.

Boolean Operations on Conic Polygons

An algorithm for Boolean operations on conic polygons is proposed. Conic polygons are polygons consisting of conic segments or bounded conics with directions. Preliminaries of Boolean operations on general polygons are presented. In our algorithm, the intersection points and the topological relationships between two conic polygons are computed. Boundaries are obtained by tracking path and selecting uncrossed boundaries following rule tables to build resulting conic polygons. We define a set of rules for the intersection, union, and subtraction operations on conic polygons. The algorithm considers degeneration cases such as homology, complement, interior, and exterior. The algorithm is also evaluated and implemented.

Fast,Exact and Robust Set Operations on Polyhedrons Using Localized Constructive Solid Geometry Trees

Regularized Boolean operations have been widely used in 3D modeling systems. However, evaluating Boolean operations may be quite numerically unstable and time consuming, especially for iterated set operations. A novel and unified technique is proposed in this paper for computing single and iterated set operations efficiently, robustly and exactly. An adaptive octree is combined with a nested constructive solid geometry （CSG） tree by this technique. The intersection handling is restricted to the cells in the octree where intersection actually occurs. Within those cells, a CSG tree template is instanced by the surfaces and the tree is converted to planebased binary space partitioning （BSP） for set evaluation; Moreover, the surface classification is restricted to the ceils in the octree where the surfaces only come from a model and are within the bounding-boxes of other polyhedrons. These two ways bring about the efficiency and scalability of the operations, in terms of runtime and memory. As all surfaces in such a cell have the same classification relation, they are classified as a whole. Robustness and exactness are achieved by integrating plane-based geometry representation with adaptive geometry predicate technique in intersection handling, and by applying divide-and-conquer arithmetic on surface classification. Experimental results demonstrate that the proposed approach can guarantee the robustness of Boolean computations and runs faster than other existing approaches.

AN ALGORITHM ACHIEVING VALID BOOLEAN OPERATION RESULTS ON POLYHEDRAL SOLIDS

A polyhedral solid modeler that operates on boundary representations (B-reps) of ob- jects must derive topological information from numerical data.Due to finite precision of the com- puter,unavoidable numerical calculation errors may result in ambiguous or contradictory decision of topology.These effects cause existing polyhedral modelers to fail when confronted with objects that nearly align or barely intersect. Based on analysing the reasons which cause the failure of Boolean operation to fail,this paper describes an algorithm using solid integrity to carefully design each step of Boolean operation,so that valid polyhedral modeling results may be achieved.

A NEW PLANAR BOOLEAN OPERATIO ALGORITHM BASED ON LINE SEGMENT SORTING

This paper presents a new method of Boolean operation First, a linesegment-polygonclassification theorem is proposed. Then, according to this theorem and basic idea for Booleanoperation, we give the discussion and apposition of the new method. At last, a typical applicationis given.

Geometrical design of variable ratio tooth profile based on Boolean subtraction operation and a novel modification method

Variable transmission ratio racks show great potential in rice transplanters as a key component of variable transmission ratio steering to balance steering portability and sensitivity.The objective of this study was to develop a novel geometrical design method to achieve quick,high-quality modeling of the free curvilinear tooth profile of a variable transmission ratio rack.First,a discrete envelope motion 3D model was established between the pinion-sector and the variable transmission ratio rack blank based on the mapping relationship between the rotation angle of the pinion-sector and the displacement of the rack,according to the variable transmission ratio function.Based on the loop Boolean subtraction operation,which removed the pinion-sector from the rack blank during all moments of the discrete motion process,the final complex changing tooth shape of the variable transmission ratio rack was enveloped.Then,since Boolean cutting residues made the variable ratio tooth surface fluctuant and eventually affected the precision of the model,this study proposed a modification method for establishing a smooth and continuous tooth profile.First,a novel fitting algorithm used approximate variable ratio tooth profile points extracted from the Boolean cutting marks and generated a series of variable ratio tooth profiles by utilizing B-spline with different orders.Next,based on a transmission stability simulation,the variable ratio tooth profile with optimal dynamic performance was selected as the final design.Finally,tests contrasting the transmission stability of the machining samples of the initial variable ratio tooth profile and the final variable ratio tooth profile were conducted.The results indicated that the final variable ratio tooth profile is more effective than the initial variable ratio tooth profile.Therefore,the proposed variable ratio tooth profile modeling and modification method for eliminating Boolean cutting residues and improving surface accuracy is proved to be feasible.

Spline R-Function and Applications in FEM

R-function is a widely used tool when considering objects obtained through the Boolean operations start from simple base primitives.However,there is square root operation in the representation.Considering that the use of splines will facilitate the calculations within the CAD system,in this paper,we propose a system of R-functions represented in spline form called Spline R-function(SR).After trans-forming the function ranges of two base primitives to a new coordinate system,a series of sign constraints following a specific Boolean operation are derived and the spline R-function can be formulated as a piecewise function.Representation of SR in both B´ezier form and B-spline form have been given.Among which the B´ezier ordinates are determined with the help of the B-net method through setting up a series of relations according to the sign constraints and properties of R-functions.The construction processes for both Boolean intersection and union operations with different smoothness are discussed in detail.Numerical experiments are conducted to show the potential of the proposed spline R-function.

Design and verification of an FPGA programmable logic element based on Sense-Switch pFLASH

This paper proposes a kind of programmable logic element(PLE)based on Sense-Switch pFLASH technology.By programming Sense-Switch pFLASH,all three-bit look-up table(LUT3)functions,partial four-bit look-up table(LUT4)functions,latch functions,and d flip flop(DFF)with enable and reset functions can be realized.Because PLE uses a choice of operational logic(COOL)approach for the operation of logic functions,it allows any logic circuit to be implemented at any ratio of combinatorial logic to register.This intrinsic property makes it close to the basic application specific integrated circuit(ASIC)cell in terms of fine granularity,thus allowing ASIC-like cell-based mappers to apply all their optimization potential.By measuring Sense-Switch pFLASH and PLE circuits,the results show that the“on”state driving current of the Sense-Switch pFLASH is about 245.52μA,and that the“off”state leakage current is about 0.1 pA.The programmable function of PLE works normally.The delay of the typical combinatorial logic operation AND3 is 0.69 ns,and the delay of the sequential logic operation DFF is 0.65 ns,both of which meet the requirements of the design technical index.