A NOVEL LOW DISTORTION HIGH LINEARITY CMOS BOOTSTRAPPED SWITCH

This paper proposes a novel low distortion high linearity CMOS bootstrapped switch, and the proposed switch can alleviate the nonlinear distortion of the on-resistance by eliminating first order signal-dependent variation of the overdrive voltage. Based on a 0.18 mm standard CMOS process, the simulation results show that at 100 MHz sampling clock frequency and 49 MHz input signal with 2Vpp, the proposed switch in differential mode has a Spurious-Free Dynamic Range(SFDR) of 90.1 dB.

A bootstrapped switch employing a new clock feed-through compensation technique

Nonlinearity caused by the clock feed-through of a bootstrapped switch and its compensation techniques are analyzed. All kinds of clock feed-through compensation configurations and their drawbacks are also investigated. It is pointed out that the delay path match of the clock boosting circuit is the critical factor that affects the effectiveness of clock feed-through compensation. Based on that, a new clock feed-through compensation configuration and corresponding bootstrapped switch are presented and designed optimally with the UMC mixed-mode/RF 0.18 μm 1P6M P-sub twin-well CMOS process by orientating and elaborately designing the switch MOSFETs that influence the delay path match of the clock boosting circuit. HSPICE simulation results show that the proposed clock feedthrough compensation configuration can not only enhance the sampling accuracy under variations of process, power supply voltage, temperature and capacitors but also decrease the even harmonic, high-order odd harmonic and THD on the whole effectively.

A High Linearity,13bit Pipelined CMOS ADC

A 13bit,pipelined analog-to-digital converter （ADC） designed to achieve high linearity is described. The high linearity is realized by using the passive capacitor error-averaging technique to calibrate the capacitor mismatch error, a gain-boosting opamp to minimize the finite gain error and gain nonlinearity,a bootstrapping switch to reduce the switch on-resistor nonlinearity, and an anti-disturb design to reduce the noise from the digital supply. This ADC is implemented in 0.18μm CMOS technology and occupies a die area of 3.2mm^2 , including pads. Measured performance includes - 0.18/ 0.15LSB of differential nonlinearity, -0.35/0.5LSB of integral nonlinearity, 75.7dB of signal-to-noise plus distortion ratio （SNDR） and 90. 5 dBc of spurious-free dynamic range （SFDR） for 2.4MHz input at 2.5MS/s. At full speed conversion （5MS/s） and for the same 2.4MHz input, the measured SNDR and SFDR are 73.7dB and 83.9 dBc, respectively. The power dissipation including output pad drivers is 21mW at 2.5MS/s and 34mW at 5MS/s,both at 2.7V supply.

An 8-bit 100-MS/s digital-to-skew converter embedded switch with a 200-ps range for time-interleaved sampling

A sampling switch with an embedded digital-to-skew converter(DSC) is presented.The proposed switch eliminates time-interleaved ADCs' skews by adjusting the boosted voltage.A similar bridged capacitors' charge sharing structure is used to minimize the area.The circuit is fabricated in a 0.18μm CMOS process and achieves sub-1 ps resolution and 200 ps timing range at a rate of 100 MS/s.The power consumption is 430μW at maximum.The measurement result also includes a 2-channel 14-bit 100 MS/s time-interleaved ADCs(TI-ADCs) with the proposed DSC switch's demonstration.This scheme is widely applicable for the clock skew and aperture error calibration demanded in TI-ADCs and SHA-less ADCs.

A 10-bit 50-MS/s sample-and-hold circuit with low distortion sampling switches

A fully-differential switched-capacitor sample-and-hold （S/H） circuit used in a 10-bit 50-MS/s pipeline analog-to-digital converter （ADC） was designed and fabricated using a 0.35-μm CMOS process. Capacitor flip-around architecture was used in the S/H circuit to lower the power consumption. In addition, a gain-boosted operational transconductance amplifier （OTA） was designed with a DC gain of 94 dB and a unit gain bandwidth of 460 MHz at a phase margin of 63 degree, which matches the S/H circuit. A novel double-side bootstrapped switch was used, improving the precision of the whole circuit. The measured results have shown that the S/H circuit reaches a spurious free dynamic range （SFDR） of 67 dB and a signal-to-noise ratio （SNR） of 62.1 dB for a 2.5 MHz input signal with 50 MS/s sampling rate. The 0.12mm^2 S/H circuit operates from a 3.3 V supply and consumes 13.6 mW.

A power-efficient 12-bit analog-to-digital converter with a novel constant-resistance CMOS input sampling switch

Apower-efficient 12-bit40-MS/spipelineanalog-to-digitalconverter（ADC）implementedina0.13 μm CMOS technology is presented. A novel CMOS bootstrapping switch, which offers a constant on-resistance over the entire input signal range, is used at the sample-and-hold front-end to enhance the dynamic performance of the pipelined ADC. By implementing with 2.5-bit-per-stage and a simplified amplifier sharing architecture between two successive pipeline stages, a very competitive power consumption and small die area can be achieved. Meanwhile, the substrate-biasing-effect attenuated T-type switches are introduced to reduce the crosstalk between the two op- amp sharing successive stages. Moreover, a two-stage gain boosted recycling folded cascode （RFC） amplifier with hybrid frequency compensation is developed to further reduce the power consumption and maintain the ADC＇s performance simultaneously. The measured results imply that the ADC achieves a spurious-free dynamic range （SFDR） of 75.7 dB and a signal-to-noise-plus-distortion ratio （SNDR） of 62.74 dB with a 4.3 MHz input signal; the SNDR maintains over 58.25 dB for input signals up to 19.3MHz. The measured differential nonlinearity （DNL） and integral nonlinearity （INL） are -0.43 to ＋0.48 LSB and -1.62 to ＋ 1.89 LSB respectively. The prototype ADC consumes 28.4 mW under a 1.2-V nominal power supply and 40 MHz sampling rate, transferring to a figure- of-merit （FOM） of 0.63 pJ per conversion-step.

High power-efficient asynchronous SAR ADC for IoT devices

This paper presents a power-efficient 100-MS/s,10-bit asynchronous successive approximation register（SAR） ADC.It includes an on-chip reference buffer and the total power dissipation is 6.8 mW.To achieve high performance with high power-efficiency in the proposed ADC,bootstrapped switch,redundancy,set-and-down switching approach,dynamic comparator and dynamic logic techniques are employed.The prototype was fabricated using 65 nm standard CMOS technology.At a 1.2-V supply and 100 MS/s,the ADC achieves an SNDR of 56.2 dB and a SFDR of 65.1 dB.The ADC core consumes only 3.1 mW,resulting in a figure of merit（FOM） of 30.27 fJ/conversionstep and occupies an active area of only 0.009 mm^2.

Design and simulation of a 12-bit,40 MSPS asynchronous SAR ADC for the readout of PMT signals

High precision and large dynamic range measurement ave required in the readout systems for the Water Cherenkov Detector Array （WCDA） in the Large High Altitude Air Shower Observatory （LHAASO）. This paper presents a prototype of a 12-bit 40 MSPS Analog-to-Digital Converter （ADC） Application Specific Integrated Circuit （ASIC） designed for the readout of the LHAASO WCDA. Combining this ADC and the front-end ASIC finished in our previous work, high precision charge measurement can be achieved based on the digital peak detection method. This ADC is implemented based on a power-efficient Successive Approximation Register （SAR） architecture, which incorporates key parts such as a Capacitive Digital-to-Analog Converter （CDAC）, dynamic compavator and asyn- chronous SAR control logic. The simulation results indicate that the Effective Number Of Bits （ENOB） with a sampling rate of 40 MSPS is better than 10 bits in an input frequency range below 20 MHz, while its core power consumption is 6.6 mW per channel. The above results are good enough for the readout requirements of the WCDA.

A single-channel 10-bit 160 MS/s SAR ADC in 65 nm CMOS

This paper demonstrates a single-channel 10-bit 160 MS/s successive-approximation-register （SAR） analog-to-digital converter （ADC） in 65 nm CMOS process with a 1.2 V supply voltage. To achieve high speed, a new window-opening logic based on the asynchronous SAR algorithm is proposed to minimize the logic delay, and a partial set-and-down DAC with binary redundancy bits is presented to reduce the dynamic comparator offset and accelerate the DAC settling. Besides, a new bootstrapped switch with a pre-charge phase is adopted in the track and hold circuits to increase speed and reduce area. The presented ADC achieves 52.9 dB signal-to-noise distortion ratio and 65 dB spurious-free dynamic range measured with a 30 MHz input signal at 160 MHz clock. The power consumption is 9.5 mW and a core die area of 250 ×200 μm^2 is occupied.

A 14-bit 100-MS/s CMOS pipelined ADC featuring 83.5-dB SFDR

This paper demonstrates a 14-bit 100 MS/s CMOS pipelined analog-to-digital converter （ADC）. The nonlinearity model for bootstrapped switches is established to optimize the design parameters of bootstrapped switches, and the calculations based on this model agree well with the measurement results. In order to achieve high linearity, a gradient-mismatch cancelling technique is proposed, which eliminates the first order gradient error of sampling capacitors by combining arrangement of reference control signals and capacitor layout. Fabricated in a 0.18-μm CMOS technology, this ADC occupies 10.16-mm2 area. With statistics-based background calibration of finite opamp gain in the first stage, the ADC achieves 83.5-dB spurious free dynamic range and 63.7-dB signalto-noise-and distortion ratio respectively, and consumes 393 mW power with a supply voltage of 2 V.

A 14-bit 50 MS/s sample-and-hold circuit for pipelined ADC

A high performance sample-and-hold （S/H） circuit used in a pipelined analog-to-digital converter （ADC） is presented. Capacitor flip-around architecture is used in this S/H circuit with a novel gain-boosted differential folded cascode operational transconductance amplifier. A double-bootstrapped switch is designed to improve the performance of the circuit. The circuit is implemented using a 0.18 μm 1P6M CMOS process. Measurement results show that the effective number of bits is 14.03 bits, the spurious free dynamic range is 94.62 dB, the signal to noise and distortion ratio is 86.28 dB, and the total harmonic distortion is -91.84 dB for a 5 MHz input signal with 50 MS/s sampling rate. A pipeline ADC with the designed S/H circuit has been implemented.

A sample and hold circuit for pipelined ADC

A high performance sample-and-hold(S/H) circuit used in a pipelined analog-to-digital converter(ADC) is presented in this paper. Fully-differential capacitor flip-around architecture was used in this S/H circuit.A gain-boosted folded cascode operational transconductance amplifier(OTA) with a DC gain of 90 dB and a GBW of 738 MHz was designed. A low supply voltage bootstrapped switch was used to improve the linearity of the S/H circuit. With these techniques, the designed S/H circuit can reach 94 dB SFDR for a 48.9 MHz input frequency with 100 MS/s sampling rate. Measurement results of a 14-bit 100-MS/s pipeline ADC with designed S/H circuit are presented.

An S/H circuit with parasitics optimized for IF-sampling

An IF-sampling S/H is presented,which adopts a flip-around structure,bottom-plate sampling technique and improved input bootstrapped switches.To achieve high sampling linearity over a wide input frequency range,the floating well technique is utilized to optimize the input switches.Besides,techniques of transistor load linearization and layout improvement are proposed to further reduce and linearize the parasitic capacitance.The S/H circuit has been fabricated in 0.18-μm CMOS process as the front-end of a 14 bit,250 MS/s pipeline ADC.For30 MHz input,the measured SFDR/SNDR of the ADC is 94.7 dB/68.5dB,which can remain over 84.3 dB/65.4dB for input frequency up to 400 MHz.The ADC presents excellent dynamic performance at high input frequency,which is mainly attributed to the parasitics optimized S/H circuit.

A 0.6-V,69-dB subthreshold sigma–delta modulator

In this paper a 0.6 V, 14 bit/500 Hz subthreshold inverter-based sigma-delta modulator is proposed. In the first integrator of the modulator, a bootstrap switch is used to accomplish accurate signal sampling. Without a transconductor operational amplifier(OTA), the sigma-delta modulator adopts a cascode inverter in the subthreshold region to save power consumption. The modulator is fabricated with a 0.13μm CMOS mixed-signal process. The experiment results show that with the 0.6 V power supply it achieves a maximum SNDR of 69.7 dB and an ENOB of 11.3 bit, respectively, but only consumes 5.07 μw power dissipation.

A low power time-interleaved 10-bit 250-MSPS charge domain pipelined ADC for IF sampling

A 10-bit 250-MSPS two-channel time-interleaved charge-domain（CD） pipelined analog-to-digital converter （ADC） is presented.MOS bucket-brigade device（BBD） based CD pipelined architecture is used to achieve low power consumption.An all digital low power DLL is used to alleviate the timing mismatches and to reduce the aperture jitter.A new bootstrapped MOS switch is designed in the sample and hold circuit to enhance the IF sampling capability.The ADC achieves a spurious free dynamic range（SFDR） of 67.1 dB,signal-to-noise ratio （SNDR） of 55.1 dB for a 10.1 MHz input,and SFDR of 61.6 dB,SNDR of 52.6 dB for a 355 MHz input at full sampling rate.Differential nonlinearity（DNL） is ＋0.5/-0.4 LSB and integral nonlineariry（INL） is ＋0.8/-0.75 LSB.Fabricated in a 0.18-μm 1P6M CMOS process,the prototype 10-bit pipelined ADC occupies 1.8×1.3 mm2 of active die area,and consumes only 68 mW at 1.8 V supply.