Integrated Experimental and Simulation Investigation of Breakdown Voltage Characteristics Across Electrode Configurations in SF_(6) Circuit Breakers

This study investigates the breakdown voltage characteristics in sulfur hexafluoride(SF6)circuit breakers,employing a novel approach that integrates both experimental investigations and finite element simulations.Utilizing a sphere-sphere electrode configuration,we meticulously measured the relationship between breakdown voltage and electrode gap distances ranging from 1 cm to 4.5 cm.Subsequent simulations,conducted using COMSOL Multiphysics,mirrored the experimental setup to validate the model’s accuracy through a comparison of the breakdown voltage-electrode gap distance curves.The simulation results not only aligned closely with the experimental data but also allowed the extraction of detailed electric field strength,electric potential contours,and electric current flow curves at the breakdown voltage for gap distances extending from 1 to 4.5 cm.Extending the analysis,the study explored the electric field and potential distribution at a constant voltage of 72.5 kV for gap distances between 1 to 10 cm,identifying the maximum electric field strength.A comprehensive comparison of five different electrode configurations(sphere-sphere,sphere-rod,sphere-plane,rod-plane,rod-rod)at 72.5 kV and a gap distance of 1.84 cm underscored the significant influence of electrode geometry on the breakdown process.Moreover,the research contrasts the breakdown voltage in SF6 with that in air,emphasizing SF6’s superior insulating properties.This investigation not only elucidates the intricate dynamics of electrical breakdown in SF6 circuit breakers but also contributes valuable insights into the optimal electrode configurations and the potential for alternative insulating gases,steering future advancements in high-voltage circuit breaker technology.

On-State Breakdown Model for High Voltage RESURF LDMOS

An analytical breakdown model under on state condition for high voltage RESURF LDMOS is proposed.The model considers the drift velocity saturation of carriers and influence of parasitic bipolar transistor.As a result,electric field profile of n drift in LDMOS at on state is obtained.Based on this model,the electric SOA of LDMOS can be determined.The analytical results partially fit to our numerical (by MEDICI) and experiment results.This model is an aid to understand the device physics during on state accurately and it also directs high voltage LDMOS design.

Breakdown Voltage and Charge to Breakdown Investigation of Gate Oxide of 0.18μm Dual Gate CMOS Process with Different Measurement Methods

Breakdown voltage （Vbd） and charge to breakdown （Qbd） are two parameters often used to evaluate gate oxide reliability. In this paper,we investigate the effects of measurement methods on Vbd and Qbd of the gate oxide of a 0.18μm dual gate CMOS process. Voltage ramps （V-ramp） and current ramps （J-ramp） are used to evaluate gate oxide reliability. The thin and thick gate oxides are all evaluated in the accumulation condition. Our experimental results show that the measurement methods affect Vbd only slightly but affect Qbd seriously,as do the measurement conditions.This affects the I-t curves obtained with the J-ramp and V-ramp methods. From the I-t curve,it can be seen that Qbd obtained using a J-ramp is much bigger than that with a V-ramp. At the same time, the Weibull slopes of Qbd are definitely smaller than those of Vbd. This means that Vbd is more reliable than Qbd, Thus we should be careful to use Qbd to evaluate the reliability of 0.18μm or beyond CMOS process gate oxide.

A High Breakdown Voltage Thin SOI Device with a Vertically Linearly Graded Concentration Drift Region

As the thickness of an SOI layer varies,a minimum breakdown voltage is reached when the thickness is about 2μm. The vertical electric field of the SOI LDMOS with a drift region which is vertically linearly graded is constant. The vertically linearly graded concentration drift can be achieved by impurity implanting followed by thermal diffusion. In this way,the vertical breakdown voltage of SOI LDMOS with 2μm thickness SOI layer can be improved by 43%. The on-state resistance is lowered by 24 % because of the higher impurity concentration of the SOI surface.

Realizing High Breakdown Voltage SJ-LDMOS on Bulk Silicon Using a Partial n-Buried Layer

A new design concept is proposed to eliminate the substrate-assisted depletion effect that significantly degrades the breakdown voltage （BV） of conventional super junction-LDMOS. The key feature of the new concept is that a partial buried layer is implemented which compensates for the charge interaction between the p-substrate and SJ region,realizing high breakdown voltage and low on-resistance. Numerical simulation results indicate that the proposed device features high breakdown voltage,low on-resistance,and reduced sensitivity to doping imbalance in the pillars. In addition, the proposed device is compatible with smart power technology.

Analytical Model of Surface Field Distribution and Breakdown Voltage for RESURF LDMOS Transistor

An analytical model of the surface field distribution and breakdown voltage of the reduced surface field lateral double diffusion MOS transistor is proposed.Based on the 2-D Poisson's equation solution,the derived model gives the closed form solutions of the surface potential and electrical field distributions as a function of the structure parameters and drain bias.A criterion for obtaining the optimal trade-off between the breakdown voltage and on-resistance is also presented to serve to quantify the maximum breakdown voltage and optimal relations of all design parameters.Analytical results are shown in good agreement with the numerical analysis obtained by the semiconductor device simulator MEDICI and previous reported experimental data.

Equivalent Doping Transformation Method for Predicting Breakdown Voltage and Peak Field at Breakdown of Epitaxial-Diffused Punch-Through Junction

Based on a new semi empirical analytical method, namely equivalent doping transformation, the breakdown voltage and the peak field of the epitaxial diffused punch through junction have been obtained. The basic principle of this method is introduced and a set of breakdown voltage and peak field plots are provided for the optimum design of the low voltage power devices. It shows that the analytical results coincide with the previous numerical simulation well.

Prediction of Breakdown Voltage of Asymmetric Linearly-Graded Junction by Equivalent Doping Profile Transformation Method

This report describes an equivalent doping profile transformation method with which the avalanche breakdown voltage of the asymmetric linearly graded junction was analytically predicted.The maximum breakdown voltage and the different depletion layer extension on the diffused side and substrate side are demonstrated in the report.The report shows the equivalent doping profile method is valid to predict the breakdown voltage of the complex P N junction.The analytical results agree with the experimental breakdown voltage in comparison with the abrupt junction and symmetric linearly graded junction approximations.

New Breakdown Electric Field Calculation for SF6 High Voltage Circuit Breaker Applications

The critical electric fields of hot SF6 are calculated including both electron and ion kinetics in wide ranges of temperature and pressure, namely from 300 K up to 4000 K and 2 atmospheres up to 32 atmospheres respectively. Based on solving a multi-term electron Boltz- mann equation the calculations use improved electron-gas collision cross sections for twelve SF6 dissociation products with a particular emphasis on the electron-vibrating molecule interactions. The ion kinetics is also considered and its role on the critical field becomes non negligible as the temperature is above 2000 K. These critical fields are then used in hydrodynamics simulations which correctly predict the circuit breaker behaviours observed in the case of breaking tests.

Breakdown voltage model and structure realization of a thin silicon layer with linear variable doping on a silicon on insulator high voltage device with multiple step field plates

Based on the theoretical and experimental investigation of a thin silicon layer（TSL） with linear variable doping（LVD） and further research on the TSL LVD with a multiple step field plate（MSFP）,a breakdown voltage（BV） model is proposed and experimentally verified in this paper.With the two-dimensional Poisson equation of the silicon on insulator（SOI） device,the lateral electric field in drift region of the thin silicon layer is assumed to be constant.For the SOI device with LVD in the thin silicon layer,the dependence of the BV on impurity concentration under the drain is investigated by an enhanced dielectric layer field（ENDIF）,from which the reduced surface field（RESURF） condition is deduced.The drain in the centre of the device has a good self-isolation effect,but the problem of the high voltage interconnection（HVI） line will become serious.The two step field plates including the source field plate and gate field plate can be adopted to shield the HVI adverse effect on the device.Based on this model,the TSL LVD SOI n-channel lateral double-diffused MOSFET（nLDMOS） with MSFP is realized.The experimental breakdown voltage（BV） and specific on-resistance（R on,sp） of the TSL LVD SOI device are 694 V and 21.3 ·mm 2 with a drift region length of 60 μm,buried oxide layer of 3 μm,and silicon layer of 0.15 μm,respectively.

A Test Study of 50% Lightning Impulse Breakdown Voltage on Rod-Plane Gap with Two-Phase Mixture of Gas and Solid Particles

A test study on 50% lightning impulse breakdown voltage in two-phase mixture of gas and solid particles has been carried out in a specially designed discharge cabinet. A mechanical sieve is set up for sifting different solid particles into the discharge space uniformly. The lightning impulse voltage according with international electro-technical commission （IEC） standard is applied to the electrodes inside the discharge cabinet by the rule of up-down method in a total of 40 times. The results showed that the 50% lightning impulse breakdown voltage in two-phase mixture of gas and solid particles has its own features and is much different from that in air.

Source-field-plated Ga_2O_3 MOSFET with a breakdown voltage of 550 V

Ga_2O_3 metal–oxide–semiconductor field-effect transistors(MOSFETs) with high-breakdown characteristics were fabricated on a homoepitaxial n-typed β-Ga_2O_3 film, which was grown by metal organic chemical vapor deposition(MOCVD) on an Fedoped semi-insulating(010) Ga_2O_3 substrate. The structure consisted of a 400 nm unintentionally doped(UID) Ga_2O_3 buffer layer and an 80 nm Si-doped channel layer. A high k HfO_2 gate dielectric film formed by atomic layer deposition was employed to reduce the gate leakage. Moreover, a source-connected field plate was introduced to enhance the breakdown characteristics. The drain saturation current density of the fabricated device reached 101 mA/mm at V_(gs) of 3 V. The off-state current was as low as 7.1 ×10^(-11) A/mm, and the drain current I_(ON)/I_(OFF) ratio reached 10~9. The transistors exhibited three-terminal off-state breakdown voltages of 450 and 550 V, corresponding to gate-to-drain spacing of 4 and 8 μm, respectively.

Closed-form breakdown voltage/specific on-resistance model using charge superposition technique for vertical power double-diffused metal–oxide–semiconductor device with high-κ insulator

An improved vertical power double-diffused metal–oxide–semiconductor（DMOS） device with a p-region（P1） and high-κ insulator vertical double-diffusion metal–oxide–semiconductor（HKP-VDMOS） is proposed to achieve a better performance on breakdown voltage（BV）/specific on-resistance（Ron,sp） than conventional VDMOS with a high-κ insulator（CHK-VDMOS）.The main mechanism is that with the introduction of the P-region,an extra electric field peak is generated in the drift region of HKP-VDMOS to enhance the breakdown voltage.Due to the assisted depletion effect of this p-region,the specific on-resistance of the device could be reduced because of the high doping density of the N-type drift region.Meanwhile,based on the superposition of the depleted charges,a closed-form model for electric field/breakdown voltage is generally derived,which is in good agreement with the simulation result within 10% of error.An HKP-VDMOS device with a breakdown voltage of 600 V,a reduced specific on-resistance of 11.5 Ωm·cm^2 and a figure of merit（FOM）（BV^2/Ron,sp）of 31.2 MW·cm^-2 shows a substantial improvement compared with the CHK-VDMOS device.

Non-depletion floating layer in SOI LDMOS for enhancing breakdown voltage and eliminating back-gate bias effect

A non-depletion floating layer silicon-on-insulator （NFL SOI） lateral double-diffused metal–oxide–semiconductor （LDMOS） is proposed and the NFL-assisted modulated field （NFLAMF） principle is investigated in this paper. Based on this principle, the floating layer can pin the potential for modulating bulk field. In particular, the accumulated high concentration of holes at the bottom of the NFL can efficiently shield the electric field of the SOI layer and enhance the dielectric field in the buried oxide layer （BOX）. At variation of back-gate bias, the shielding charges of NFL can also eliminate back-gate effects. The simulated results indicate that the breakdown voltage （BV） is increased from 315 V to 558 V compared to the conventional reduced surface field （RESURF） SOI （CSOI） LDMOS, yielding a 77% improvement. Furthermore, due to the field shielding effect of the NFL, the device can maintain the same breakdown voltage of 558 V with a thinner BOX to resolve the thermal problem in an SOI device.

Collector optimization for tradeoff between breakdown voltage and cut-off frequency in SiGe HBT

As is well known, there exists a tradeoff between the breakdown voltage BVcEO and the cut-off frequency fT for a standard heterojunction bipolar transistor （HBT）. In this paper, this tradeoff is alleviated by collector doping engineering in the SiGe HBT by utilizing a novel composite of P＋ and N- doping layers inside the collector-base （CB） space-charge region （SCR）. Compared with the single N-type collector, the introduction of the thin P＋ layers provides a reverse electric field weakening the electric field near the CB metallurgical junction without changing the field direction, and the thin N layer further effectively lowers the electric field near the CB metallurgical junction. As a result, the electron temperature near the CB metallurgical junction is lowered, consequently suppressing the impact ionization, thus BVcEO is improved with a slight degradation in fT. The results show that the product of fTXBVcEo is improved from 309.51 GHz.V to 326.35 GHz.V.

An AlGaN/GaN HEMT with a reduced surface electric field and an improved breakdown voltage

A reduced surface electric field in an AlGaN/GaN high electron mobility transistor （HEMT） is investigated by employing a localized Mg-doped layer under the two-dimensional electron gas （2-DEG） channel as an electric field shaping layer. The electric field strength around the gate edge is effectively relieved and the surface electric field is distributed evenly as compared with those of HEMTs with conventional source-connected field plate and double field plate structures with the same device physical dimensions. Compared with the HEMTs with conventional sourceconnected field plates and double field plates, the HEMT with a Mg-doped layer also shows that the breakdown location shifts from the surface of the gate edge to the bulk Mg-doped layer edge. By optimizing both the length of Mg-doped layer, Lm, and the doping concentration, a 5.5 times and 3 times the reduction in the peak electric field near the drain side gate edge is observed as compared with those of the HEMTs with source-connected field plate structure and double field plate structure, respectively. In a device with VGS = -5 V, Lm 1.5 m, a peak Mg doping concentration of 8×10^17 cm-3 and a drift region length of 10 m, the breakdown voltage is observed to increase from 560 V in a conventional device without field plate structure to over 900 V without any area overhead penalty.

A novel high breakdown voltage and high switching speed GaN HEMT with p-GaN gate and hybrid AlGaN buffer layer for power electronics applications

A novel p-GaN gate GaN high-electron-mobility transistor(HEMT)with an AlGaN buffer layer and hybrid dielectric zone(H-HEMT)is proposed.The hybrid dielectric zone is located in the buffer and composed of horizontal arranged HfO2 zone and SiNx zone.The proposed H-HEMT is numerically simulated and optimized by the Silvaco TCAD tools(ATLAS),and the DC,breakdown,C-V and switching properties of the proposed device are characterized.The breakdown voltage of the proposed HEMT is significantly improved with the introduction of the hybrid dielectric zone,which can effectively modulate the electric field distribution in the GaN channel and the buffer.High breakdown voltage of 1490 V,low specific on-state resistance of 0.45 mΩ·cm2 and high Baliga's figure of merit(FOM)of 5.3 GW/cm2,small R onQ oss of 212 mΩ·nC,high turn-on speed 627 V/ns and high turn-off speed 87 V/ns are obtained at the same time with the gate-to-drain distance L gd of 6μm.

Improving breakdown voltage performance of SOI power device with folded drift region

A novel silicon-on-insulator（SOI） high breakdown voltage（BV） power device with interlaced dielectric trenches（IDT） and N/P pillars is proposed. In the studied structure, the drift region is folded by IDT embedded in the active layer,which results in an increase of length of ionization integral remarkably. The crowding phenomenon of electric field in the corner of IDT is relieved by the N/P pillars. Both traits improve two key factors of BV, the ionization integral length and electric field magnitude, and thus BV is significantly enhanced. The electric field in the dielectric layer is enhanced and a major portion of bias is borne by the oxide layer due to the accumulation of inverse charges（holes） at the corner of IDT.The average value of the lateral electric field of the proposed device reaches 60 V/μm with a 10 μm drift length, which increases by 200% in comparison to the conventional SOI LDMOS, resulting in a breakdown voltage of 607 V.

Terminal-optimized 700-V LDMOS with improved breakdown voltage and ESD robustness

A novel terminal-optimized triple RESURF LDMOS(TOTR-LDMOS) is proposed and verified in a 0.25-μm bipolarCMOS-DMOS(BCD) process. By introducing a low concentration region to the terminal region, the surface electric field of the TOTR-LDMOS decreases, helping to improve the breakdown voltage(BV) and electrostatic discharge(ESD) robustness. Both traditional LDMOS and TOTR-LDMOS are fabricated and investigated by transmission line pulse(TLP) tests,direct current(DC) tests, and TCAD simulations. The results show that comparing with the traditional LDMOS, the BV of the TOTR-LDMOS increases from 755 V to 817 V without affecting the specific on-resistance(R_(on,sp)) of 6.99Ω·mm^(2).Meanwhile, the ESD robustness of the TOTR-LDMOS increases by 147%. The TOTR-LDMOS exhibits an excellent performance among the present 700-V LDMOS devices.

Enhancement of Breakdown Voltage in AlGaN/GaN High Electron Mobility Transistors Using Double Buried p-Type Layers

A novel A1GaN/GaN high electron mobility transistor （HEMT） with double buried p-type layers （DBPLs） in the GaN buffer layer and its mechanism are studied. The DBPL A1GaN/GaN HEMT is characterized by two equi-long p-type GaN layers which are buried in the GaN buffer layer under the source side. Under the condition of high-voltage blocking state, two reverse p-n junctions introduced by the buried p-type layers will effectively modulate the surface and bulk electric fields. Meanwhile, the buffer leakage is well suppressed in this structure and both lead to a high breakdown voltage. The simulations show that the breakdown voltage of the DBPL structure can reach above 2000 V from 467 V of the conventional structure with the same gate-drain length of 8μm.