High Sensitivity Digital Instantaneous Frequency Measurement Receiver for Precise Frequency Analysis

There are numerous applications, such as Radar, that leverage wideband technology. However, the presence of noise introduces certain limitations and challenges. It is crucial to harness wideband technology for applications demanding the rapid and precise transmission of diverse information from one point to another within a short timeframe. The ability to report a signal without tuning within the input bandwidth stands out as one of the advantages of employing a digital wideband receiver. As indicated, a digital wideband receiver plays a pivotal role in achieving high precision and accuracy. The primary distinction between Analog and Digital Instantaneous Frequency Measurement lies in the fact that analog Instantaneous Frequency Measurement (IFM) receivers have traditionally covered extensive input bandwidths, reporting one accurate frequency per short pulse. In the contemporary landscape, digital IFM systems utilize high-sampling-rate Analog-to-Digital Converters (ADC) along with Hilbert transforms to generate two output channels featuring a 90-degree phase shift. This paper explores the improvement of sensitivity in current digital IFM receivers. The optimization efforts target the Hilbert transform and autocorrelations architectures, aiming to refine the system’s ability to report fine frequencies within a noisy wide bandwidth environment, thereby elevating its overall sensitivity.

Efficient structures for wideband digital receiver

Digital receivers have become more and more popular in radar, communication, and electric warfare for the advantages compared with their analog counterparts. But conventional digital receivers have been generally considered impractical for bandwidth greater than several hundreds MHz. To extend receiver bandwidth, decrease data rate and save hardware resources, three novel structures are proposed. They decimate the data stream prior to mixing and filtering, then process the multiple decimated streams in parallel at a lower rate. Consequently it is feasible to realize wideband receivers on the current ASIC devices. A design example and corresponding simulation results are demonstrated to evaluate the proposed structures.

Design and simulation of digital channelized receivers in fractional Fourier domain

An approach is proposed to realize a digital channelized receiver in the fractional Fourier domain （FRFD） for signal intercept applications. The presented architecture can be considered as a generalization of that in the traditional Fourier domain. Since the linear frequency modulation （LFM） signal has a good energy concentration in the FRFD, by choosing an appropriate fractional Fourier transform （FRFT） order, the presented architecture can concentrate the broadband LFM signal into only one sub-channel and that will prevent it from crossing several sub-channels. Thus the performance of the signal detection and parameter estimation after the sub-channel output will be improved significantly. The computational complexity is reduced enormously due to the implementation of the polyphase filter bank decomposition, thus the proposed architecture can be realized as efficiently as in the Fourier domain. The related simulation results are presented to verify the validity of the theories and methods involved in this paper.

Design and Implementation of Partial Shared Digital Channelized Receiver

A novel efficient partial sharing channelization structure with odd and even stacking is designed and implemented. There are two special designs in the proposed structure. Firstly, by the intensive channel overlap design, for non-cooperative wideband signals, the proposed structure can achieve good parameter estimation accuracy and high probability of complete interception.Secondly, based on the partial sharing design developed in this paper, the computation burden of the proposed structure can be greatly reduced compared with the traditional directly implemented structures. Experiments and numerical simulations are conducted to evaluate the proposed structure, which shows its improvements over traditional methods in terms of field programmable gate arrays(FPGA) resource consumption and parameter estimation accuracy.

Digital AGC Based on Coherent Adjustment Cycle for DSSS Receiver

In order to meet the requirements for zero value stability of direct sequence spread spectrum(DSSS) signal processing in high dynamic scenario,digital automatic gain control(AGC) is employed to regulate power.However,conventional AGC causes degradation in the synchronization performance of DSSS receiver.Based on the theoretical analysis of the influence of digital AGC on DSSS signal synchronization,this paper proposes a new AGC algorithm,which is applicable to multi-channel digital DSSS signal receiver.By making power adjustment cycle and synchronization cycle coherent with each other adaptively,the influence of digital AGC on subsequent synchronization processing has been eliminated.Theoretical analysis,simulation results and experimental data verify the validity of the proposed algorithm.By virtue of the proposed algorithm,the influence of digital AGC on DSSS signal synchronization is eliminated.This algorithm applies to an aerospace engineering project successfully.

Design and Implementation of a Cueing Wideband Digital EW Receiver

A cueing wideband digital Electronic Warfare （EW） receiver is presented. The proposed receiver, which is to measure the instantaneous frequency and bandwidth of the intercept short-duration pulse radar signals that cue and match the corresponding ones, meets the requirements of good sensitivity and dynamic range for EW and can save hardware resources greatly as well. In addition, real-time signal processing, which is the main bottleneck for covering a wide instantaneous frequency band for EW receiver, is better solved in the proposed design structure. The highly efficient implementation and good parameter estimation algorithms are proposed as welL Theoretical analysis and experimental results show that this structure is feasible.

Digital Receiver for Laser Imaging Radar

With the extension of the application domains for laser imaging radar, it is necessary to find a new technical way to obtain high technical performance and adaptive ability. In this paper, A new concept of digital receiver of laser imaging radar system is presented. This digital receiver is defined as a time varying parameter receiver which possesses large dynamics region and time domain filter. The receiver’s mode, component structure as well as every function of its processing are described. The results and laboratorial data show the feasibility of digital reception. Also, it can exploit the inherent nature of laser imaging radar to obtain high probability of detection.

DESIGN OF INTERPOLATION FILTER FOR ALL DIGITAL RECEIVER-ON THE INTERPOLATION PROBLEM OF FULL RESPONSE MODULATION SIGNALS

All digital implementation of receiver is a main topic on digital communication recently. The design of interpolation filter is one of the important problems for all digital implementation of receiver. In this paper, for full response linear modulation signal, a interpolation criterion is proposed. An interpolation formula is presented on bandwidth-limited transmission signal. For example, using the raised cosine roll off function as the system pulse response, the feasibility and effectiveness on the interpolation formula are certified by theoretical and numerical analysis. The computer simulation result on 16-QAM signal is given.

Research for the Dynamic Range and Its Extension of Digital Intermediate Frequency Receiver

For the optimization of dynamic range and bandwidth of digital intermediate frequency receiver(DIFR), main factors affecting them and their relationships are studied. Firstly, the DIFR sensitivity, bandwidth, noise factor of radio frequency (RF) analog front-end (RFAF), and processing gain of intermediate frequency(IF) sampling are analyzed. Secondly, the constraint relationship of the noise factor of RFAF, the signal-to-noise ratio of ADC and the dynamic range of DIFR are studied. The relationship between the dynamic range and the RFAF gain, and that of the extended dynamic range and the RF AGC(automatic gain control) step are educed and simulated. These results can be used as theory foundations and design references for the implementation and optimization of the large dynamic range and wideband DIFR.

Normalized Design of Multi-channel LIF Digital Receiver

A design method for parallel processing application on multi-channel low-intermediate-frequency(LIF) digital receiver was presented. It is based on the DSP sub-array with a simple topology and operation timing to evaluate and determine the processing capability and then construct the parallel processing array for multi-channel signals according to the restriction of operation timing. Using this method, the design of multi-channel digital receiver may be simplified. Finally, a design example was used to show how to apply this method.

A Novel Receiver Architecture for DBF Antenna Array

The developments of the high speed analog to digital converters （ADC） and advanced digital signal processors （DSP） make the smart antenna with digital beamforming （DBF） a reality. In conventional M-elements array antenna system, each element has its own receiving channel and ADCs. In this paper, a novel smart antenna receiver with digital beamforming is proposed. The essential idea is to realize the digital beamforming receiver based on bandpass sampling of multiple distinct intermediate frequency （IF） signals. The proposed system reduces receiver hardware from M IF channels and 2M ADCs to one IF channel and one ADC using a heterodyne radio frequency （RF） circuitry and a multiple bandpass sampling digital receiver. In this scheme, the sampling rate of the ADC is much higher than the summation of the M times of the signal bandwidth. The local oscillator produces different local frequency for each RF channel The receiver architecture is presented in detail, and the simulation of bandpass sampling of multiple signals and digital down conversion to baseband is given. The principle analysis and simulation results indicate the effectiveness of the new proposed receiver.

Design of Si-bipolar Monolithic Main Amplifier IC for Optical Fiber Receivers

A broadband amplifier with transadmittance and transimpedance stages is designed and two types of improved AGC amplifiers are developed on the base of theory study. Making use of the basic amplifier cells, a main amplifier IC for optical-fiber receivers is deliberated. By computer simulating the performances of the designed main amplifier meet the necessity of high gain and wide dynamic range . They are maximum voltage gain of 42 dB, the bandwidth of 730 MHz,the input signal( V p-p )range from 5 mV to 1 V,the output amplitude about 1 V, the dynamic range of 46 dB. The designed circuit containing no inductance and large capacitance will be convenient for realizing integration. A monolithic integrated design of 622 Mb/s main amplifier is completed.

AN EFFICIENT IMPLEMENTATION ARCHITECTURE FOR WIDE-BAND DIGITAL DOWNCONVERSION

The wide-band digital receiving systems require digital downconversion(DDC) with high data rate and short tuning time in order to intercept the narrow-band signals within broad tuning bandwidth. But these requirements can not be met by the commercial DDC. In this paper an efficient implementation architecture is presented. It combines the flexibility of DFT tuning with the efficiency of the polyphase filter bank decomposition. By first decimating the data prior to filtering and mixing, this architecture gives a better solution to the mismatch between the lower hardware speed and high data rate. The computer simulations show the feasibility of this processing architecture.

Development of China Digital Seismological Observational Systems

Development of China Digital Seismological Observational Systems during 1996~2000 and the Capital Circle Area Seismograph Network during 1999~2001 are introduced, and the station distributions, instruments used, main tasks of National Digital Seismograph Network, Regional Digital Seismograph Network and Portable Digital Seismograph Network are introduced chiefly.

A Low Power Non-Volatile LR-WPAN Baseband Processor with Wake-Up Identification Receiver

The paper proposes a low power non-volatile baseband processor with wake-up identification(WUI) receiver for LR-WPAN transceiver.It consists of WUI receiver,main receiver,transmitter,non-volatile memory(NVM) and power management module.The main receiver adopts a unified simplified synchronization method and channel codec with proactive Reed-Solomon Bypass technique,which increases the robustness and energy efficiency of receiver.The WUI receiver specifies the communication node and wakes up the transceiver to reduce average power consumption of the transceiver.The embedded NVM can backup/restore the states information of processor that avoids the loss of the state information caused by power failure and reduces the unnecessary power of repetitive computation when the processor is waked up from power down mode.The baseband processor is designed and verified on a FPGA board.The simulated power consumption of processor is 5.1uW for transmitting and 28.2μW for receiving.The WUI receiver technique reduces the average power consumption of transceiver remarkably.If the transceiver operates 30 seconds in every 15 minutes,the average power consumption of the transceiver can be reduced by two orders of magnitude.The NVM avoids the loss of the state information caused by power failure and energy waste caused by repetitive computation.

A Parallel Amplifier Structure for Increasing Dynamic Range of EW Receivers

In Electronic Warfare （EW） receivers, the desired Dynamic Range （DR） often far exceeds the dynamic range attainable with available Analog-to-Digital Converter （ADC） technology. ADC is the key bottleneck in achieving the needed dynamic range. In this paper, an approach for improving the effective DR by utiliTing multiple amplifiers is presented. The amplifiers, arranged in parallel channels with different gains, can increase the dynamic range greatly.

A programmable gain amplifier with digitally assisted DC offset calibration for a direct-conversion WLAN receiver

This paper presents a programmable gain amplifier（PGA） circuit with a digitally assisted DC offset cancellation（DCOC） scheme for a direct conversion WLAN receiver.Implemented in a standard 0.13-μm CMOS process,the PGA occupies 0.39 mm2 die area and dissipates 6.5 mW power from a 1.2 V power supply.By using a single loop single digital-to-analog converter（DAC） mixed signal DC offset cancellation topology,the minimum DCOC settling time achieved is as short as 1.6μs with the PGA gain ranging from -8 to 54 dB in a 2 dB step.The DCOC loop utilizes a segmented DAC structure to lower the design complexity without sacrificing accuracy and a digital control algorithm to dynamically set the DCOC loop to fast or normal response mode,making the PGA circuit in compliance with the targeted WLAN specifications.

Investigation of HTSC digital trunking communication receiver subsystem

The application of HTSC (high temperature superconductor) microwave devices in a UHF digital trunking communication system is introduced.The replacement between the HTSC microwave devices and the normal microwave devices is conducted.The digital sensitivity of the base station in complex electromagnetic environment has been increased to 6 dB,as the results of the experiment indicated,and this means that the coverage radius of the base station has been improved about twice,that is to say,the coverage area can be extended to four times as large as that of the current method.

MCS HOG Features and SVM Based Handwritten Digit Recognition System

Digit Recognition is an essential element of the process of scanning and converting documents into electronic format. In this work, a new Multiple-Cell Size (MCS) approach is being proposed for utilizing Histogram of Oriented Gradient (HOG) features and a Support Vector Machine (SVM) based classifier for efficient classification of Handwritten Digits. The HOG based technique is sensitive to the cell size selection used in the relevant feature extraction computations. Hence a new MCS approach has been used to perform HOG analysis and compute the HOG features. The system has been tested on the Benchmark MNIST Digit Database of handwritten digits and a classification accuracy of 99.36% has been achieved using an Independent Test set strategy. A Cross-Validation analysis of the classification system has also been performed using the 10-Fold Cross-Validation strategy and a 10-Fold classification accuracy of 99.26% has been obtained. The classification performance of the proposed system is superior to existing techniques using complex procedures since it has achieved at par or better results using simple operations in both the Feature Space and in the Classifier Space. The plots of the system’s Confusion Matrix and the Receiver Operating Characteristics (ROC) show evidence of the superior performance of the proposed new MCS HOG and SVM based digit classification system.