Positive Bias Temperature Instability Degradation of Buried InGaAs Channel nMOSFETs with InGaP Barrier Layer and Al2O3 Dielectric

Positive bias temperature instability stress induced interface trap density in a buried InGaAs channel metaloxide-semiconductor field-effect transistor with a InCaP barrier layer and Al2O3 dielectric is investigated. Well behaved split C-V characteristics with small capacitance frequency dispersion are confirmed after the insertion of the InCaP barrier layer. The direct-current Id-Vg measurements show both degradations of positive gate voltage shift and sub-threshold swing in the sub-threshold region, and degradation of positive △Vg in the oncurrent region. The Id-Vg degradation during the positive bias temperature instability tests is mainly contributed by the generation of near interface acceptor traps under stress. Specifically, the stress induced aeceptor traps contain both permanent and recoverable traps. Compared with surface channel InCaAs devices, stress induced recoverable donor traps are negligible in the buried channel ones.

Improvement of Operation Characteristics for MONOS Charge Trapping Flash Memory with SiGe Buried Channel

We propose and investigate a novel metal/SiO_2/Si_3N_4/SiO_2/SiGe charge trapping flash memory structure（named as MONOS）, utilizing Si Ge as the buried channel. The fabricated memory device demonstrates excellent programerasable characteristics attributed to the fact that more carriers are generated by the smaller bandgap of Si Ge during program/erase operations. A flat-band voltage shift 2.8 V can be obtained by programming at ＋11 V for 100 us. Meanwhile, the memory device exhibits a large memory window of ~7.17 V under ±12 V sweeping voltage, and a negligible charge loss of 18% after 104 s＇ retention. In addition, the leakage current density is lower than 2.52 × 10^（-7） A·cm^（-2） below a gate breakdown voltage of 12.5 V. Investigation of leakage current-voltage indicates that the Schottky emission is the predominant conduction mechanisms for leakage current. These desirable characteristics are ascribed to the higher trap density of the Si_3N_4 charge trapping layer and the better quality of the interface between the SiO_2 tunneling layer and the Si Ge buried channel. Therefore, the application of the Si Ge buried channel is very promising to construct 3 D charge trapping NAND flash devices with improved operation characteristics.