With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced mi...With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.展开更多
As new technologies emerge data centers and servers have established themselves as one of the largest and fastest growing consumers of power.While switched capacitor converter topologies have some very attractive feat...As new technologies emerge data centers and servers have established themselves as one of the largest and fastest growing consumers of power.While switched capacitor converter topologies have some very attractive features,namely low reliance on magnetic components and high efficiency,several critical factors have prevented their adoption in high current data center applications.The family of converters proposed are novel intermediate bus converter that demonstrates the highest performance yet achieved for 48 V to 12 V conversion with up to 2.5 kW/in^(3) power density,higher than 99% peak efficiency,and 97.2% full load efficiency for 12 V/70 A output.The reduction of voltage stress across the MOSFETs as well as extremely low reliance on magnetics are the key driving factors behind this high efficiency and power density,and are achieved without a sensitive resonant design or the usage of complex control technique.展开更多
文摘With the rapid development of integrated circuit(IC)technology,reusable intelligent property(IP)core design is widely valued by the industry.Based on the in-depth study of the functional characteristics of advanced microcontroller bus architecture(AMBA),a design scheme of IP core is presented,and it is divided into the functional modules,and the structural design of the IP core is completed.The relationship between the internal modules of the IP core is clarified,and the top-down design method is used to build the internal architecture of the IP core.The IP core interface module,register module,baud rate module,transmit module,receive module,and interrupt module are designed in detail by using Verilog language.The simulation results show that the designed IP core supports serial peripheral interface(SPI)protocol,the function coverage of IP core reaches 100%,the maximum working frequency reaches 200 MHz,and the resource occupancy rate is less than 15%.The reusable IP core can support multiple data formats,multiple timing transmission modes,and master/slave operation modes,reducing the resource consumption of hardware circuits and having stronger applicability.
文摘As new technologies emerge data centers and servers have established themselves as one of the largest and fastest growing consumers of power.While switched capacitor converter topologies have some very attractive features,namely low reliance on magnetic components and high efficiency,several critical factors have prevented their adoption in high current data center applications.The family of converters proposed are novel intermediate bus converter that demonstrates the highest performance yet achieved for 48 V to 12 V conversion with up to 2.5 kW/in^(3) power density,higher than 99% peak efficiency,and 97.2% full load efficiency for 12 V/70 A output.The reduction of voltage stress across the MOSFETs as well as extremely low reliance on magnetics are the key driving factors behind this high efficiency and power density,and are achieved without a sensitive resonant design or the usage of complex control technique.