文章介绍了槟松紫外全帧背照式面阵CCD(S7171-0909)的结构和工作特点,分析了该芯片驱动时序要求;采用可编程逻辑器件EP2C8作为硬件平台,在Quartus II 9.1软件环境下,用基于状态机的算法对时序电路进行了描述,设计产生了芯片正常工作所...文章介绍了槟松紫外全帧背照式面阵CCD(S7171-0909)的结构和工作特点,分析了该芯片驱动时序要求;采用可编程逻辑器件EP2C8作为硬件平台,在Quartus II 9.1软件环境下,用基于状态机的算法对时序电路进行了描述,设计产生了芯片正常工作所需的时序脉冲信号,并选用EL7202作为CCD驱动器对时钟脉冲进行功率放大。调用第三方软件进行仿真,并给出实际工作输出波形,结果表明,设计的时序电路满足CCD对各驱动信号的要求。展开更多
The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip....The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.展开更多
文摘文章介绍了槟松紫外全帧背照式面阵CCD(S7171-0909)的结构和工作特点,分析了该芯片驱动时序要求;采用可编程逻辑器件EP2C8作为硬件平台,在Quartus II 9.1软件环境下,用基于状态机的算法对时序电路进行了描述,设计产生了芯片正常工作所需的时序脉冲信号,并选用EL7202作为CCD驱动器对时钟脉冲进行功率放大。调用第三方软件进行仿真,并给出实际工作输出波形,结果表明,设计的时序电路满足CCD对各驱动信号的要求。
基金National High Technology Research and Development Program of China(863 Program)(No.2009AA7010102)
文摘The time delay integration charge coupled device(TDI CCD)is the key component in remote sensing systems.The paper analyzes the structure and the working principles of the device according to a customized TDI CCD chip.Employing the special clock resources and large-scale phase locked logic(PLL)in field-programmable gate arrays(FPGA),a timing-driven approach is proposed,using which all timing signals including reset gate,horizontal and vertical timing signals,are implemented in one chip.This not only reduces printed circuit board(PCB)space,but also enhances the portability of the system.By studying and calculating CCD parameters thoroughly,load capacity and power consumption,package,etc,are compared between various candidates chips,and detailed comparison results are also listed in table.Experimental results show that clock generator and driving circuit satisfy the requirements of high speed TDI CCD.
