A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-co...A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio (SINR) at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.展开更多
随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相...随着以太网技术和集成电路技术的发展,以太网物理层(Physical Layer,PHY)芯片的速率和性能都得到了极大提升,电路复杂度更是几何级增长,以至于常规的自动测试设备(Automatic Test Equipment,ATE)测试很难充分验证其功能,所以亟需开展相应测试方法研究。提出了一种高效的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法。该方法以ZYNQ MPSOC为核心,设计了一种直达应用层面的系统级测试装置,从而减少了与物理层直接交互的行为,有效降低了测试装置及程序开发难度。经试验验证,提出的基于ZYNQ MPSOC的以太网PHY芯片功能测试方法能够用于以太网PHY芯片测试。展开更多
This work is focused on the structure design of MMSE linear equalizers in the downlink of CDMA-based multi-user communication systems. Previous work was mostly focused on the performance comparison between ZF and MMSE...This work is focused on the structure design of MMSE linear equalizers in the downlink of CDMA-based multi-user communication systems. Previous work was mostly focused on the performance comparison between ZF and MMSE linear equalizers and the conclusion is that the performance based on MMSE criterion is much better than that based on ZF one. In this paper, we only discuss MMSE equalizer and a new block structure of MMSE linear equalizer is derived from the traditional structure of this kind of equalizer. Furthermore, a block MMSE linear equalizer is improved through using the overlap-save technique. Simulation results shaw that the average performance of improved block MMSE linear equalizers is better than those of the block MMSE equalizers and traditional MMSE equalizers. At the same time, the computation complexity of all these MMSE equalizers is given. It is shown that the comple:rity of proposed block MMSE equalizers is lower than that of the traditional equalizers with optimal delay, D, when the length of the filter in traditional MMSE equalizers equals the block size of block MMSE equalizers.展开更多
文摘A chip-level space-time equalization receiver scheme is proposed for multiple-input multiple-output high-speed downlink packet access (MIMO HSDPA) systems to jointly combat the co-channel interference and the inter-code interference. A fractional sample equalizer is also derived to further improve the performance of the receiver. Performance analysis and the calculation of the output signal to interference ratio (SINR) at each receiver antenna are presented to help direct the design of equalization weight in a more optimal manner. System simulations demonstrate the significant performance gain over conventional Rake receiver and high potential of MIMO HSDPA for high-data-rate packet transmission.
文摘This work is focused on the structure design of MMSE linear equalizers in the downlink of CDMA-based multi-user communication systems. Previous work was mostly focused on the performance comparison between ZF and MMSE linear equalizers and the conclusion is that the performance based on MMSE criterion is much better than that based on ZF one. In this paper, we only discuss MMSE equalizer and a new block structure of MMSE linear equalizer is derived from the traditional structure of this kind of equalizer. Furthermore, a block MMSE linear equalizer is improved through using the overlap-save technique. Simulation results shaw that the average performance of improved block MMSE linear equalizers is better than those of the block MMSE equalizers and traditional MMSE equalizers. At the same time, the computation complexity of all these MMSE equalizers is given. It is shown that the comple:rity of proposed block MMSE equalizers is lower than that of the traditional equalizers with optimal delay, D, when the length of the filter in traditional MMSE equalizers equals the block size of block MMSE equalizers.