CIC Filter Theory in DDC and Implementation by Using FPGA

Cascade Integrator Comb(CIC) filter is the main part of the next generation High Frequency (HF) radar. This paper describes the key points of CIC theory in the Digital Down Conversion (DDC) module of a radar receiver, and takes advantage of the high flexibility and high density feature of Field Programmable Gate Array (FPGA) for putting forth to design the CIC filter by using FPGA. This paper provides particular insight into design by FPGA, which has advantages in high speed operation and simply structure. Some important and practical applications are given in this paper. The simulation result proves the validity and veracity. Because we can adjust the parameters freely according to our need, the CIC filter can be adapted to the next generation HF radar. Key words FPGA - DDC - CIC filter - HF radar CLC number TN 47 Foundation item: Supported by the 863 High Technology Project of China(2001AA631050)Biography: MA Zhi-gang(1978-), male, Ph. D candidate, research direction: software radio and EDA design.

On design of efficient comb decimator with improved response

A three-part comb decimator is presented in this paper, for the applications with severe requirements of circuit performance and frequency response. Based on the modified prime factorization method and multistage polyphase decomposition, an efficient non-recursive structure for the cascaded integrator-comb （CIC） decimation filter is derived. Utilizing this structure as the core part, the proposed comb decimator can not only loosen the decimation ratio＇s limitation, but also balance the tradeoff among the overall power consumption, circuit area and maximum speed. Further, to improve the frequency response of the comb decimator, a cos-prefilter is introduced as the preprocessing part for increasing the aliasing rejection, and an optimum sin-based filter is used as the compensation part for decreasing the passband droop.