A Statistical Method for Characterizing CMOS Process Fluctuations in Subthreshold Current Mirrors

A novel method to characterize CMOS process fluctuations in subthreshold current mirrors （SCM） is reported. The proposed model is succinct in methodology and calculation complexity compared with previous statistical models. However,it provides favorable estimations of CMOS process fluctuations on the SCM circuit, which makes it promising for engineering applications. The model statistically abstracts physical parameters, which depend on the IC process, into random variables with certain mean values and standard deviations, while aggregating all the random impacts into a discrete martingale. The correctness of the proposed method is experimentally verified on an SCM circuit implemented in an SMIC 0.18μm CMOS 1P6M mixed signal process with a conversion factor of 100 in an input range from 100pA to lμA. The pro- posed theory successfully predicts - 10% of die-to-die fluctuation measured in the experiment, and also suggests the -lmV of threshold voltage standard deviation over a single die,which meets the process parameters suggested by the design kit from the foundry. The deviations between calculated probabilities and measured data are less than 8%. Meanwhile, pertinent suggestions concerning high fluctuation tolerance subthreshold analog circuit design are also made and discussed.

High-Voltage MOSFETs in a 0.5μm CMOS Process

There is growing interest in developing high-voltage MOSFET devices that can be integrated with low-voltage CMOS digital and analog circuits. In this paper,high-voltage nand p-type MOSFETs are fabricated in a commercial 3.3/ 5V 0.5μm n-well CMOS process without adding any process steps using n-well and p-channel stops. High current and highvoltage transistors with breakdown voltages between 23 and 35V for the nMOS transistors with different laydut parameters and 19V for the pMOS transistors are achieved. This paper also presents the insulation technology and characterization results for these high-voltage devices.

A 1.2 V,3.1%3σ-accuracy thermal sensor analog front-end circuit in 12 nm CMOS process

This paper presents a 1.2 V high accuracy thermal sensor analog front-end circuit with 7 probes placed around the microprocessor chip.This analog front-end consists of a BGR(bandgap reference),a DEM(dynamic element matching)control,and probes.The BGR generates the voltages linear changed with temperature,which are followed by the data read out circuits.The superior accuracy of the BGR’s output voltage is a key factor for sensors fabricated via the FinFET digital process.Here,a 4-stage folded current bias structure is proposed,to increase DC accuracy and confer immunity against FinFET process variation due to limited device length and low current bias.At the same time,DEM is also adopted,so as to filter out current branch mismatches.Having been fabricated via a 12 nm FinFET CMOS process,200 chips were tested.The measurement results demonstrate that these analog front-end circuits can work steadily below 1.2 V,and a less than 3.1%3σ-accuracy level is achieved.Temperature stability is 0.088 mV/℃across a range from-40 to 130℃.

A novel integrated ultraviolet photodetector based on standard CMOS process

A novel integrated ultraviolet（UV） photodetector has been proposed, which realizes a high UV selectivity by combining a conventional UV-selective photodiode with an extra infrared（IR） photodiode. The IR photodiode is designed for compensating the photocurrent response of the UV photodiode in the infrared band and is 15 times smaller than the UV one. The integrated photodetector has been fabricated in a 0.35 μm standard CMOS technology. Some critical performance indices of this new structure photodetector, such as spectral responsivity, breakdown voltage, quenching waveform, and transient response, are measured and analyzed. Test results show that the complementary UV–IR photodetector has a maximum spectral responsivity of 0.27 A·W-1 at the wavelength of 400 nm. The device has a high UV selectivity of 3000,which is much higher than that of the single UV photodiode.

A Q-Enhanced CMOS RF Filter for Multi-Band Wireless Communications

An RF bandpass filter with a Q-enhancement active inductor is presented. The design technique for a tunable Q-enhancement CMOS active inductor operating in the wide RF-band is described. Moreover,issues related to noise and stability of the active inductor are explained. The filter was fabricated in 0.18μm CMOS technolo- gy,and the circuit occupied an active area of only 150μm ×200μm. Measurement results show that the filter centered at 2. 44GHz with about 60MHz bandwidth （3dB） is tunable in center frequency from about 2.07 to 2. 44GHz. The ldB compression point is - 15dBm while consuming 10. 8mW of DC power,and a maximum quality factor of 103 is attained at the center frequency of 2.07GHz.

Monolithically Integrated Optoelectronic Receivers Implemented in 0.25μm MS/RF CMOS

A monolithically integrated optoelectronic receiver is presented. A silicon-based photo-diode and receiver circuits are integrated on identical substrates in order to eliminate the parasitics induced by hybrid packaging. Implemented in the present deep sub-micron MS/RF （mixed signal, radio frequency） CMOS,this monolithically OEIC takes advantage of several new features to improve the performance of the photo-diode and eventually the whole OEIC.

A New Low Voltage RF CMOS Mixer Design

A new architecture of CMOS low voltage downconve rsion mixer is presented.With 1.452GHz LO input and 1.45GHz RF input,simulation results show that the conversion gain is 15dB,IIP3 is -4.5dBm,NF is 17dB,the maximum transient power dissipation is 9.3mW,and DC power dissipation is 9.2mW.The mixer’s noise and linearity analyses are also presented.

A nano-metallic-particles-based CMOS image sensor for DNA detection

In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 gm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.

A Low-Power,Single-Poly,Non-Volatile Memory for Passive RFID Tags

Single-poly,576bit non-volatile memory is designed and implemented in an SMIC 0.18μm standard CMOS process for the purpose of reducing the cost and power of passive RFID tag chips. The memory bit cell is designed with conventional single-poly pMOS transistors, based on the bi-directional Fowler-Nordheim tunneling effect, and the typical program/erase time is 10ms for every 16bits. A new ,single-ended sense amplifier is proposed to reduce the power dissipation in the current sensing scheme. The average current consumption of the whole memory chip is 0.8μA for the power supply voltage of 1.2V at a reading rate of 640kHz.

Automatic IQ Phase Calibration Design in a 2.4GHz Direct Conversion Receiver

An automatic IQ phase calibration method implemented in a 2.4GHz direct conversion receiver is proposed. It uses a delay locked loop （DLL） with a proposed quadrature phase detector to greatly reduce the phase error. The receiver is fabricated in a 0.18μm CMOS process. Measurements show that the IQ phase error can be calibrated within 1°,which satisfies the system requirement.

A novel monolithic ultraviolet image sensor based on a standard CMOS process

We present a monolithic ultraviolet（UV） image sensor based on a standard CMOS process.A compact UV sensitive device structure is designed as a pixel for the image sensor.This UV image sensor consists of a CMOS pixel array,high-voltage switches,a readout circuit and a digital control circuit.A 16×16 image sensor prototype chip is implemented in a 0.18μm standard CMOS logic process.The pixel and image sensor were measured. Experimental results demonstrate that the image sensor has a high sensitivity of 0.072 V/（mJ/cm^2） and can capture a UV image.It is suitable for large-scale monolithic bio-medical and space applications.

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available,especially no high density capacitor.To address this problem,a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process.This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal（MIM） capacitor regarding their capacitor density.Detailed simulations are carried out for the leakage,the voltage dependency,the temperature dependency,and the quality factor between an inter-metal shuffled（IMS） capacitor and an MIM capacitor.Finally,an IMS capacitor is chosen to perform the inter-stage matching.The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application.The PA occupies 370 × 200 μm^2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

CMOS vision sensor with fully digital image process integrated into low power 1/8-inch chip

A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise （FPN） reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit （I2C） interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW.

Improved two-dimensional responsivity physical model of a CMOS UV and blue-extended photodiode

A CMOS UV and blue-extended photodiode is presented and fabricated for light detection in the ultraviolet/blue spectral range. An octagon homocentric ring-shaped geometry is used to improve the ultraviolet responsivity and suppress edge breakdown. This paper has established a two-dimensional responsivity physical model for the presented photodiode and given some numerical analyses. The dead layer effect, which is caused by the high-doping effects and boron redistribution, is considered when analyzing the distribution of the current of the proposed UV and blue-extended photodiode. In the dead layer, the boron doping profile decreases towards the surface. Simulated results illustrate that the responsivity in the UV range is obviously decreased by the effect of the dead layer, while it is not affected in the visible and near-infrared part of the spectrum. The presented photodiode is fabricated and the silicon tested results are given, which agree well with the simulated ones.

A millimeter wave linear superposition oscillator in 0.18 m CMOS technology

This paper presents a millimeter wave （mm-wave） oscillator that generates signal at 36.56 GHz. The ram-wave oscillator is realized in a UMC 0.18 μm CMOS process. The linear superposition （LS） technique breaks through the limit of cut-off frequency （JET）, and realizes a much higher oscillation than Jr. Measurement results show that the LS oscillator produces a calibrated 37.17 dBm output power when biased at 1.8 V; the output power of fundamental signal is -10.85 dBm after calibration. The measured phase noise at 1 MHz frequency offset is -112.54 dBc/Hz at the frequency of 9.14 GHz. This circuit can be properly applied to mm-wave communication systems with advantages of low cost and high integration density.

A high efficiency charge pump circuit for low power applications

A high efficiency charge pump circuit is designed and realized. The charge transfer switch is biased by the additional capacitor and transistor to eliminate the influence of the threshold voltage. Moreover, the bulk of the switch transistor is dynamically biased so that the threshold voltage gets lower when it is turned on during charge transfer and gets higher when it is turned off. As a result, the efficiency of the charge pump circuit can be improved. A test chip has been implemented in a 0.18μm 3.3 V standard CMOS process. The measured output voltage of the eight-pumpingstage charge pump is 9.8 V with each pumping capacitor of 0.5 pF at an output current of 0.18 μA, when the clock frequency is 780 kHz and the supply voltage is 2 V. The charge pump and the clock driver consume a total current of 2.9 μA from the power supply. This circuit is suitable for low power applications.

High linearity current communicating passive mixer employing a simple resistor bias

A high linearity current communicating passive mixer including the mixing cell and transimpedance amplifier(TIA) is introduced.It employs the resistor in the TIA to reduce the source voltage and the gate voltage of the mixing cell.The optimum linearity and the maximum symmetric switching operation are obtained at the same time.The mixer is implemented in a 0.25μm CMOS process.The test shows that it achieves an input third-order intercept point of 13.32 dBm,conversion gain of 5.52 dB,and a single sideband noise figure of 20 dB.