Incomplete charge transfer in CMOS image sensor caused by Si/SiO_(2)interface states in the TG channel

CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in the charge transfer path,which reduces the charge transfer efficiency and image quality.Until now,scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition.However,the existing models have thus far ignored the charge transfer limitation due to Si/SiO_(2)interface state traps in the transfer gate channel,particularly under low illumination.Therefore,this paper proposes,for the first time,an analytical model for quantifying the incomplete charge transfer caused by Si/SiO_(2)interface state traps in the transfer gate channel under low illumination.This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution,exponential distribution and measured distribution.The model was verified with technology computer-aided design simulations,and the results showed that the simulation results exhibit the consistency with the proposed model.

Column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor

High linearity and low noise column readout chain are two key factors in CMOS image sensor.However,offset mismatch and charge sharing always exist in the conventional column wise readout implementation,even adopting the technology of correlated double sample.A simple column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor is proposed in this paper.Based on the bottom plate sampling and fixed common level method,this novel design can avoid the offset nonuniformity between the two buffers.Also,the single buffer and switched capacitor technique can effectively suppress the charge sharing caused by the varied operating point.The proposed approach is experimentally verified in a 1024×1024 prototype chip designed and fabricated in 55 nm low power CMOS process.The measurement results show that the linear range is extended by 20%,the readout noise of bright and dark fields is reduced by 40%and 30%respectively,and the improved photo response nonuniformity is up to 1.16%.Finally,a raw sample image taken by the prototype sensor shows the excellent practical performance.

Novel CMOS image sensor pixel to improve charge transfer speed and efficiency by overlapping gate and temporary storage diffusing node

A novel CMOS image sensor(CIS) pinned photodiode(PPD) pixel, named as O-T pixel, is proposed and investigated by TCAD simulations. Compared with the conventional PPD pixel, the proposed pixel features the overlapping gate(OG)and the temporary storage diffusing(TSD) region, based on which the several-nanosecond-level charge transfer could be achieved and the complete charge transfer from the PPD to the floating node(FD) could be realized. And systematic analyses of the influence of the doping conditions of the proposed processes, the OG length, and the photodiode length on the transfer performances of the proposed pixel are conducted. Optimized simulation results show that the total charge transfer time could reach about 5.862 ns from the photodiode to the sensed node and the corresponding charge transfer efficiency could reach as high as 99.995% in the proposed pixel with 10 μm long photodiode and 2.22 μm long OG. These results demonstrate a great potential of the proposed pixel in high-speed applications.

New Active Digital Pixel Circuit for CMOS Image Sensor

A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2 μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.

High Speed Column-Parallel CDS/ADC Circuit with Nonlinearity Compensation for CMOS Image Sensors

A high speed column-parallel CDS/ADC circuit with nonlinearity compensation is proposed in this paper.The correlated double sampling (CDS) and analog-to-digital converter (ADC) functions are integrated in a threephase column-parallel circuit based on two floating gate inverters and switched-capacitor network.The conversion rate of traditional single-slope ADC is speeded up by dividing quantization to coarse step and fine step.A storage capacitor is used to store the result of coarse step and locate the section of ramp signal of fine step,which can reduce the clock step from 2 n to 2 (n/2+1).The floating gate inverters are implemented to reduce the power consumption.Its induced nonlinear offset is cancelled by introducing a compensation module to the input of inverter,which can equalize the coupling path in three phases of the proposed circuit.This circuit is designed and simulated for CMOS image sensor with 640×480 pixel array using Chartered 0.18μm process.Simulation results indicate that the resolution can reach 10-bit and the maximum frame rate can reach 200 frames/s with a main clock of 10MHz.The power consumption of this circuit is less than 36.5μW with a 3.3V power supply.The proposed CDS/ADC circuit is suitable for high resolution and high speed image sensors.

Dark output characteristic of γ-ray irradiated CMOS digital image sensors

The quality of dark output images from the CMOS (complementarymetal oxide semiconductor) black and white (B & W) digital imagesensors captured before and after γ-ray irradiation was studied. Thecharacteristic parameters of the dark output images captured atdifferent radiation dose, e.g. average brightness and itsnon-uniformity of dark out- put images, were analyzed by our testsoftware. The primary explanation for the change of the parameterswith the radi- ation dose was given.

A nano-metallic-particles-based CMOS image sensor for DNA detection

In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 gm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.

Pixel and Column Fixed Pattern Noise Suppression Mechanism in CMOS Image Sensor

A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64×64 CIS and successfully fabricated with chartered 0.35 μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier.

Modeling random telegraph signal noise in CMOS image sensor under low light based on binomial distribution

The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result,the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated,and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures.

Difference in electron-and gamma-irradiation effects on output characteristic of color CMOS digital image sensors

Changes of the average brightness and non-uniformity of dark output images,and quality of pictures captured under natural lighting for the color CMOS digital image sensorsirradiated at different electron doses have been studied in comparison to those from theγ-irradiated sensors. For the electron-irradiated sensors, the non-uniformity increases obviouslyand a small bright region on the dark image appears at the dose of 0.4 kGy. The average brightnessincreases at 0.4 kGy, increases sharply at 0.5 kGy. The picture is very blurry only at 0.6 kGy,showing the sensor undergoes severe performance degradation. Electron radiation damage is much moresevere than γ radiation damage for the CMOS image sensors. A possible explanation is presented inthis paper.

A low-power high-quality CMOS image sensor using 1.5 V 4T pinned photodiode and dual-CDS column-parallel single-slope ADC

This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD.Dual-CDS is used to reduce random noise and the nonuniformity between columns.Dual-mode counting method is proposed to improve circuit robustness.A prototype sensor was fabricated using a 0.11μm CMOS process.Measurement results show that the lag of the five-finger shaped pixel is reduced by 80%compared with the conventional rectangular pixel,the chip power consumption is only 36 mW,the dynamic range is 67.3 dB,the random noise is only 1.55 e^(-)_(rms),and the figure-of-merit is only 1.98 e^(-)·nJ,thus realizing low-power and high-quality imaging.

10-Bit Single-Slope ADC with Error Calibration for TDI CMOS Image Sensor

A 10-bit single-slope analog-to-digital converter (ADC) for time-delay-integration CMOS image sensor was proposed. A programmable ramp generator was applied to accomplish the error calibration and improve the linearity. The ADC was fabricated in a 180 nm 1P4M CMOS process. Experimental results indicate that the differential nonlinearity and integral nonlinearity were 0.51/-0.53 LSB and 0.63/-0.71 LSB, respectively. The sampling rate of the ADC was 32 kHz.

Complete Focal Plane Compression Based on CMOS Image Sensor Using Predictive Coding

In this paper, a CMOS image sensor(CIS) is proposed, which can accomplish both decorrelation and entropy coding of image compression directly on the focal plane. The design is based on predictive coding for image decorrelation. The predictions are performed in analog domain by 2×2 pixel units. Both the prediction residuals and original pixel values are quantized and encoded in parallel. Since the residuals have a peak distribution around zero,the output codewords can be replaced by the valid part of the residuals' binary mode. The compressed bit stream is accessible directly at the output of CIS without extra disposition. Simulation results show that the proposed approach achieves a compression rate of 2. 2 and PSNR of 51 on different test images.

In-Pixel Charge Addition Scheme Applied in Time-Delay Integration CMOS Image Sensors

An addition scheme applicable to time-delay integration (TDI) CMOS image sensor is proposed,which adds signals in the charge domain in the pixel array.A two-shared pixel structure adopting two-stage charge transfer is introduced,together with the rolling shutter with an undersampling readout timing.Compared with the conventional TDI addition methods,the proposed scheme can reduce the addition operations by half in the pixel array,which decreases the power consumption of addition circuits outside the pixel array.The timing arrangement and pixel structure are analyzed in detail.The simulation results show that the proposed pixel structure can achieve the charge addition with negligible nonlinearity,therefore the power consumption of the periphery addition circuits can be reduced by half theoretically.

320×240 Pixels CMOS Digital Image Sensor with Wide Dynamic Range

A 320×240 CMOS image sensor is demonstrated,which is implemented by a standard 0.6 μm 2P2M CMOS process.For reducing the chip area,each 2×2-pixel block shares a sample/hold circuit,analog-to-digital converter and 1-b memory.The 2×2 pixel pitch has an area of 40 μm×40 μm and the fill factor is about 16%.While operating at a low frame rate,the sensor dissipates a very low power by power-management circuit making pixel-level comparators in an idle state.A digital correlated double sampling,which eliminates fixed pattern noise,improves SNR of the sensor, and multiple sampling operations make the sensor have a wide dynamic range.

面向高帧率CMOS图像传感器的12位列级全差分SAR/SS ADC设计

针对高帧率CMOS图像传感器的应用需求,提出一种结合逐次逼近型(Successive Approximation Register,SAR)和单斜坡(Single Slope,SS)结构的混合型模拟数字转换器(Analog to Digital Converter,ADC)。该ADC的分辨率为12位,其中SAR ADC实现高6位量化,SS ADC实现低6位量化。该ADC采用了全差分结构消除采样开关的固定失调并减少非线性误差,同时在SAR ADC中采用了异步逻辑电路进一步缩短转换周期。采用110 nm 1P4M CMOS工艺对该电路进行了设计和版图实现,后仿真结果表明,在20 MHz的时钟下,转换周期仅为3.3μs,无杂散动态范围为77.12 dB,信噪失真比为67.38 dB,有效位数为10.90位。

基于CMOS图像传感器的复合型中子照相电子学系统的研制

针对高能物理实验中高通量、高性能的中子探测需求,本文提出了一种基于CMOS图像传感器的复合型中子照相电子学系统。该系统采用Kintex-7系列的FPGA作为系统逻辑处理的核心器件,利用SiPM的快响应为CMOS图像传感器提供快门触发,使其对光纤光锥投影的中子光斑进行曝光。通过SiPM提供的粗位置信息确定CMOS传感器的感兴趣区域,读出数据传输至上位机进行显示与分析。实验结果表明,该系统中最小像素单元尺寸为28μm×28μm的CMOS传感器能够对孔径为200μm的小孔进行成像,最大偏移为28μm,系统最高计数率为82 kHz,可实现高效率的中子探测。

高速大像素CMOS图像传感器中钳位光电二极管形状设计的研究进展

采用钳位光电二极管(PPD)的CMOS图像传感器,由于其优异的性能,已成为图像传感领域中占主导地位的技术。然而,更大尺寸PPD的应用在电荷传输速度和效率方面存在挑战,特别是在微光、高速探测的场景中,传统的像素设计难以满足必要的性能标准。一种有效的方法是通过PPD的形状设计来提升大像素性能。首先全面概述了产生PPD横向电场的两种机制:边缘电场设计和钳位电压调制,并探讨了基于这两种设计策略的各种设计改进。然后总结了传输栅-浮空扩散(TG-FD)节点收集结构及像素整体布局优化的相关研究进展。此外,还研究了PPD的形状设计对暗电流的影响。通过全面分析PPD形状设计中采用的方法,为提升大像素设计提供了参考。

基于粗细量化并行与TDC混合的CMOS图像传感器列级ADC设计方法

针对传统单斜式模数转换器(Analog-to-Digital Converter,ADC)和串行两步式ADC在面向大面阵CMOS(Complementary Metal Oxide Semiconductor)图像传感器读出过程中的速度瓶颈问题,本文提出了一种用于高速CMOS图像传感器的全并行ADC设计方法.该方法基于时间共享和时间压缩思想,将细量化时间提前到粗量化时间段内,解决了传统方法的时间冗余问题;同时采用插入式时间差值TDC(Time-to-Digital Converter),实现了全局低频时钟下的快速转换机制.本文基于55-nm 1P4M CMOS工艺对所提方法完成了详细电路设计和全面测试验证,在模拟电压3.3 V,数字电压1.2 V,时钟频率250 MHz,输入电压1.2~2.7 V的情况下,将行时间压缩至825 ns,ADC的微分非线性和积分非线性分别为+0.6/-0.6LSB和+1.6/-1.2LSB,信噪失真比(Signal-to-Noise-and-DistortionRatio,SNDR)为68.271 dB,有效位数(Effective Numbers Of Bits,ENOB)达到11.0489 bit,列不一致性低于0.05%.相比现有的先进ADC,本文提出的方法在保证低功耗、高精度的同时,ADC转换速率提高了87.1%以上,为高速高精度CMOS图像传感器的读出与量化提供了一定的理论支撑.

Exploration of high-speed 3.0 THz imaging with a 65 nm CMOS process

This paper describes a promising route for the exploration and development of 3.0 THz sensing and imaging with FET-based power detectors in a standard 65 nm CMOS process.Based on the plasma-wave theory proposed by Dyakonov and Shur,we designed high-responsivity and low-noise multiple detectors for monitoring a pulse-mode 3.0 THz quantum cascade laser(QCL).Furthermore,we present a fully integrated high-speed 32×32-pixel 3.0 THz CMOS image sensor(CIS).The full CIS measures 2.81×5.39 mm^(2) and achieves a 423 V/W responsivity(Rv)and a 5.3 nW integral noise equivalent power(NEP)at room temperature.In experiments,we demonstrate a testing speed reaching 319 fps under continuous-wave(CW)illumina-tion of a 3.0 THz QCL.The results indicate that our terahertz CIS has excellent potential in cost-effective and commercial THz imaging and material detection.