Total ionizing dose effect modeling method for CMOS digital-integrated circuit

Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID effects in complementary metaloxide semiconductor(CMOS)digital ICs based on the input/output buffer information specification(IBIS)was proposed.The digital IC was first divided into three parts based on its internal structure:the input buffer,output buffer,and functional area.Each of these three parts was separately modeled.Using the IBIS model,the transistor V-I characteristic curves of the buffers were processed,and the physical parameters were extracted and modeled using VHDL-AMS.In the functional area,logic functions were modeled in VHDL according to the data sheet.A golden digital IC model was developed by combining the input buffer,output buffer,and functional area models.Furthermore,the golden ratio was reconstructed based on TID experimental data,enabling the assessment of TID effects on the threshold voltage,carrier mobility,and time series of the digital IC.TID experiments were conducted using a CMOS non-inverting multiplexer,NC7SZ157,and the results were compared with the simulation results,which showed that the relative errors were less than 2%at each dose point.This confirms the practicality and accuracy of the proposed modeling method.The TID effect model for digital ICs developed using this modeling technique includes both the logical function of the IC and changes in electrical properties and functional degradation impacted by TID,which has potential applications in the design of radiation-hardening tolerance in digital ICs.

Testability Analysis at Switch Level for CMOS Circuits

In this paper we propose a controllability and observability measure at switch level for CMOS circuits based on the cost analysis approach.The complexity of the algorithm is nearly linear.

Development of 0.50μm CMOS Integrated Circuits Technology

Submicron CMOS IC technology, including triple layer resist lithography technology, RIE, LDD, Titanium Salicide, shallow junction, thin gate oxide, no bird's beak isolation and channel's multiple implantation doping technology have been developed. 0.50μm. CMOS integrated circuits have been fabricated using this submicron CMOS process.

Design of Multivalued Circuits Based on an Algebra for Current-Mode CMOS Multivalued Circuits

An algebra proposed for current-mode CMOS multivalued circuits is briefly reviewed. This paper discusses its application in the design of multivalued circults. Several current-mode CMOS quaternary and quinary circuits are de-signed by algebraic means. The design method based on this algebra may offer a design simpler than the previously knowll ones.

Novel High PSRR Current Reference Based on Subthreshold MOSFETs

This paper takes full advantages of the I-V transconductance characteristics of metal-oxide semiconductor field effect transistor （MOSFET） operating in the subthreshold region and the enhancement pre-regulator technique with the high gain negative feedback loop. The proposed reference circuit, designed with the SMIC 0.18 μm standard complementary metal-oxide semiconductor （CMOS） logic process technology, exhibits a stable current of about 1.701 μA with much low temperature coefficient （TC） of 2.5×10^-4μA/℃ in the temperature range of-40 to 150℃ at 1.5 V supply voltage, and also achieves a best PSRR over a broad frequency. The PSRR is about - 126 dB at DC frequency and remains -92 dB at the frequency higher 100 MHz. Moreover the proposed reference circuit operates stably at the supply voltage higher 1.2 V and has good process compatibility.

An approach to predicting dynamic power dissipation of coupled interconnect network in dynamic CMOS logic circuits

In deep submicron (DSM) integrated circuits (IC), coupling capacitors between interconnects become dominant over grounded capacitors. As a result, the dynamic power dissipation of one node is no longer only in relation to the signal on that node, and it also depends on signals on its neighbor nodes through coupling capacitors. Thus, for their limitation in dealing with ca-pacitively coupled nets, past jobs on power estimation are facing rigorous challenges and need to be ameliorated. This paper proposes and proves a simple and fast approach to predicting dynamic power dissipation of coupled interconnect networks: a coupling capacitor in dynamic CMOS logic circuits is decoupled and mapped into an equivalent cell containing an XOR gate and a grounded capacitor, and the whole circuit after mapping, consuming the same power as the original one, could be easily managed by generally-used gate-level power estimation tools. This paper also investigates the correlation coefficient method (CCM). Given the signal probabilities and the correlation coefficients between signals, the dynamic power of interconnect networks can be calculated by using CCM. It can be proved that the decoupling method and CCM draw identical results, that is to say, the decoupling method implicitly preserves correlation properties between signals and there is no accuracy loss in the decoupling process. Moreover, it is addressed that the coupling capacitors in static CMOS circuits could be decoupled and mapped into an equivalent cell containing a more complicated logic block, and the power can be obtained by the probability method for dynamic CMOS logic circuits.

Low-Power CMOS VCO with Dual-Band Local Oscillating Signal Outputs for 5/2.5-GHz WLAN Transceivers

The paper describes a low-power CMOS voltage-controlled oscillator (VCO) with dual-band local oscillating (LO) signal outputs for 5/2.5-GHz wireless local area network (WLAN) transceivers. The VCO is based on an on-chip symmetrical spiral inductor and a differential varactor. The 2.5-GHz quadrature LO signals are generated using the injection-locked frequency divider (ILFD) technique. The ILFD structure is similar to the VCO structure with its wide tracking range. The design tool ASITIC was used to optimize all on-chip symmetrical inductors. The power consumption was kept low with differential LC tanks and the ILFD technique. The circuit was implemented in a 0.18-μm CMOS process. Hspice and SpectreRF simulations show the proposed circuit could generate low phase noise 5/2.5-GHz dual band LO signals with a wide tuning range. The 2.5-GHz LO signals are quadrature with almost no phase and amplitude errors. The circuit consumes less than 5.3 mW in the tuning range with a power supply voltage of 1.5 V. The die area is only 1.0 mm×1.0 mm.

A high performance 90 nm CMOS SAR ADC with hybrid architecture

A 10-bit 2.5 MS/s SAR A/D converter is presented. In the circuit design, an R-C hybrid architecture D/A converter, pseudo-differential comparison architecture and low power voltage level shiflers are utilized. Design challenges and considerations are also discussed. In the layout design, each unit resistor is sided by dummies for good matching performance, and the capacitors are routed with a common-central symmetry method to reduce the nonlinearity error. This proposed converter is implemented based on 90 nm CMOS logic process. With a 3.3 V analog supply and a 1.0 V digital supply, the differential and integral nonlinearity are measured to be less than 0.36 LSB and 0.69 LSB respectively. With an input frequency of 1.2 MHz at 2.5 MS/s sampling rate, the SFDR and ENOB are measured to be 72.86 dB and 9.43 bits respectively, and the power dissipation is measured to be 6.62 mW including the output drivers. This SAR A/D converter occupies an area of 238× 214 μm^2. The design results of this converter show that it is suitable for multi-supply embedded SoC applications.

Low threshold voltage light-emitting diode in silicon-based standard CMOS technology

Low-voltage silicon （Si）-based light-emitting diode （LED） is designed based on the former research of LED in Si-based standard complementary metal oxide semiconductor （CMOS） technology. The low-voltage LED is designed under the research of cross-finger structure LEDs and sophisticated structure enhanced LEDs for high efficiency and stable light source of monolithic chip integration. The device size of low-voltage LED is 45.85x38.4 （#m）, threshold voltage is 2.2 V in common condition, and temperature is 27 ~C. The external quantum efficiency is about 10-6 at stable operating state of 5 V and 177 mA.

New CMOS readout circuit with background suppression and CDS for infrared focal plane array applications

A high injection, large dynamic range, stable detector bias, small area and low power consumption CMOS readout circuit with background current suppression and correlated double sampling (CDS) for a high-resolution infrared focal plane array applications is proposed. The detector bias error in this structure is less than 0.1 mV. The input resistance is ideally zero, which is important to obtain high injection efficiency. Unit-cell occupies 10 μm× 15 μm area and consumes less than 0.4 mW power. Charge storage capacity is 3 × 108 electrons. The function and performance of the proposed readout circuit have been verified by experimental results.

All-CMOS temperature compensated current reference

This paper presents a novel temperature independent current reference based on the theory of mutual compensation of mobility and threshold voltage.It is completely compatible with standard CMOS-technology.The experiment results indicate that the temperature coefficient of this current reference is less than 290 ppm/℃over a temperature range from-20 to 110℃.

A fully integrated CMOS super-regenerative wake-up receiver for EEG applications

A fully integrated super-regenerative wake-up receiver for wireless body area network applications is presented. The super-regeneration receiver is designed to receive OOK-modulated data from the base station. A low power waveform generator is adopted both to provide a quench signal for VCO and to provide a clock signal for the digital module. The receiver is manufactured in 0.18 μm CMOS process and the active area is 0.67 mm^2.It achieves a sensitivity of -80 d Bm for 10^（-3）BER with a data rate of 200 kbps. The power consumption of the super-regenerative wake-up receiver is about 2.16 m W.

A 10-bit low power SAR A/D converter based on 90 nm CMOS

Traditional and some recently reported low power,high speed and high resolution approaches for SAR A/D converters are discussed.Based on SMIC 65 nm CMOS technology,two typical low power methods reported in previous works are validated by circuit design and simulation.Design challenges and considerations for high speed SAR A/D converters are presented.Moreover,an R–C combination based method is also addressed and a 10-bit SAR A/D converter with this approach is implemented in SMIC 90 nm CMOS process.The DNL and INL are measured to be less than 0.31 LSB and 0.59 LSB respectively.With an input frequency of 420 kHz at 1 MS/s sampling rate, the SFDR and ENOB are measured to be 67.6 dB and 9.46 bits respectively,and the power dissipation is measured to be just 3.17 mW.

A common-gate bootstrapped CMOS rectifier for VHF isolated DC-DC converter

A common-gate bootstrapped CMOS rectifier dedicated for VHF（very high frequency） isolated DCDC converter is proposed.It uses common-gate bootstrapped technique to compensate the power loss due to the threshold voltage,and to solve the reflux problem in the conventional rectifier circuit.As a result,it improves the power conversion efficiency（PCE） and voltage conversion ratio（VCR）.The design saves almost 90%of the area compared to a previously reported double capacitor structure.In addition,we compare the previous rectifier with the proposed common-gate bootstrapped rectifier in the case of the same area;simulation results show that the PCE and VCR of the proposed structure are superior to other structures.The proposed common-gate bootstrapped rectifier was fabricated by using CSMC 0.5 μm BCD process.The measured maximum PCE is 86%and VCR achieves 77%at the operating frequency of 20 MHz.The average PCE is about 79%and average VCR achieves71%in the frequency range of 30-70 MHz.Measured PCE and VCR have been improved compared to previous results.

8.64-11.62 GHz CMOS VCO and divider in a zero-IF 802.11a/b/g WLAN and Bluetooth application

A fully integrated VCO and divider implemented in SMIC 0.13μm RFCMOS 1P8M technology with a 1.2 V supply voltage is presented. The frequency of the VCO is tuning from 8.64 to 11.62 GHz while the quadrature LO signals for 802.1 1 a WLAN in 5.8 GHz band or for 802.1 1b/g WLAN and Bluetooth in 2.4 GHz band can be obtained by a frequency division by 2 or 4, respectively. A 6 bit switched capacitor array is applied for precise tuning of all necessary frequency bands. The testing results show that the VCO has a phase noise of-113 dBc @ 1 MHz offset from the cartier of 5.5 GHz by dividing VCO output by two and the VCO core consumes 3.72 mW. The figure-of-merit for the tuning-range （FOMT） of the VCO is -192.6 dBc/Hz.

Accurate metamodels of device parameters and their applications in performance modeling and optimization of analog integrated circuits

Techniques for constructing metamodels of device parameters at BSIM3v3 level accuracy are presented to improve knowledge-based circuit sizing optimization. Based on the analysis of the prediction error of analytical performance expressions, operating point driven （OPD） metamodels of MOSFETs are introduced to capture the circuit＇s characteristics precisely. In the algorithm of metamodel construction, radial basis functions are adopted to interpolate the scattered multivariate data obtained from a well tailored data sampling scheme designed for MOSFETs. The OPD metamodels can be used to automatically bias the circuit at a specific DC operating point. Analytical-based performance expressions composed by the OPD metamodels show obvious improvement for most small-signal performances compared with simulation-based models. Both operating-point variables and transistor dimensions can be optimized in our nesting-loop optimization formulation to maximize design flexibility. The method is successfully applied to a low-voltage low-power amplifier.

CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission

A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm;and the power consumption is 0.5 mW.The test results show that it can work correctly.

An investigation of the DC and RF performance of InP DHBTs transferred to RF CMOS wafer substrate

This paper investigated the DC and RF performance of the In P double heterojunction bipolar transistors（DHBTs）transferred to RF CMOS wafer substrate.The measurement results show that the maximum values of the DC current gain of a substrate transferred device had one emitter finger,of 0.8μm in width and 5μm in length,are changed unobviously,while the cut-off frequency and the maximum oscillation frequency are decreased from 220to 171 GHz and from 204 to 154 GHz,respectively.In order to have a detailed insight on the degradation of the RF performance,small-signal models for the In P DHBT before and after substrate transferred are presented and comparably extracted.The extracted results show that the degradation of the RF performance of the device transferred to RF CMOS wafer substrate are mainly caused by the additional introduced substrate parasitics and the increase of the capacitive parasitics induced by the substrate transfer process itself.

A 10-bit 200-kS/s SAR ADC IP core for a touch screen SoC

Based on a 5 MSBs （most-significant-bits）-plus-5 LSBs （least-significant-bits） C-R hybrid D/A conver sion and low-offset pseudo-differential comparison approach, with capacitor array axially symmetric layout topology and resistor string low gradient mismatch placement method, an 8-channel 10-bit 200-kS/s SAR ADC （successiveapproximation-register analog-to-digital converter） IP core for a touch screen SoC （system-on-chip） is implemented in a 0.18 μm 1P5M CMOS logic process. Design considerations for the touch screen SAR ADC are included. With a 1.8 V power supply, the DNL （differential non-linearity） and INL （integral non-linearity） of this converter are measured to be about 0.32 LSB and 0.81 LSB respectively. With an input frequency of 91 kHz at 200-kS/s sampling rate, the spurious-free dynamic range and effective-number-of-bits are measured to be 63.2 dB and 9.15 bits respectively, and the power is about 136 μW. This converter occupies an area of about 0.08 mm^2. The design results show that it is very suitable for touch screen SoC applications.

Reverse current reduction of Ge photodiodes on Si without post-growth annealing

A new approach to reduce the reverse current of Ge pin photodiodes on Si is presented, in which an i-Si layer is inserted between Ge and top Si layers to reduce the electric field in the Ge layer. Without post- growth annealing, the reverse current density is reduced to -10 mA/cm^2 at -1 V, i.e., over one order of magnitude lower than that of the reference photodiode without i-Si layer. However, the responsivity of the photodiodes is not severely compromised. This lowered-reverse-current is explained by band-pinning at the i-Si/i-Ge interface. Barrier lowering mechanism induced by E-field is also discussed. The presented ＂non-thermal＂ approach to reduce reverse current should accelerate electronics-photonics convergence by using Oe on the Si complementary metal oxide semiconductor （CMOS） platform.