High Performance 70nm CMOS Devices

A high performance 70nm CMOS device has been demonstrated for the first time in the continent, China. Some innovations in techniques are applied to restrain the short channel effect and improve the driving ability, such as 3nm nitrided oxide, dual poly Si gate electrode, novel super steep retrograde channel doping by heavy ion implantation, ultra shallow S/D extension formed by Ge PAI(Pre Amorphism Implantation) plus LEI(Low Energy Implantation), thin and low resistance Ti SALICIDE by Ge PAI and special cleaning, etc. The shortest channel length of the CMOS device is 70nm. The threshold voltages, G m and off current are 0 28V,490mS·mm -1 and 0 08nA/μm for NMOS and -0 3V,340mS·mm -1 and 0 2nA/μm for PMOS, respectively. Delays of 23 5ps/stage at 1 5V, 17 5ps/stage at 2 0V and 12 5ps/stage at 3V are achieved in the 57 stage unloaded 100nm CMOS ring oscillator circuits.

Bi-CMOS技术进展(下)

三、Bi-CMOS模拟/数字电路 随着电子系统复杂性的增加以及对可靠性要求的提高,过去那种将模拟电路和数字电路通过PC板互连起来的方法已经不适应。因此,实现A/D LSI已经成为人们追求的目标。这种芯片不仅在数字通讯、测量仪器、图像处理等方面有广泛用途,而且在民用领域,如照像机的自动曝光、录相机的自动聚焦、马达控制、声音的合成和识别等方面也有广阔的市场。

Impact of the displacement damage in channel and source/drain regions on the DC characteristics degradation in deep-submicron MOSFETs after heavy ion irradiation

This paper mainly reports the permanent impact of displacement damage induced by heavy-ion strikes on the deepsubmicron MOSFETs. Upon the heavy ion track through the device, it can lead to displacement damage, including the vacancies and the interstitials. As the featured size of device scales down, the damage can change the dopant distribution in the channel and source/drain regions through the generation of radiation-induced defects and thus have significant impacts on their electrical characteristics. The measured results show that the radiation-induced damage can cause DC characteristics degradations including the threshold voltage, subthreshold swing, saturation drain current, transconductanee, etc. The radiation-induced displacement damage may become the dominant issue while it was the secondary concern for the traditional devices after the heavy ion irradiation. The samples are also irradiated by Co- 60 gamma ray for comparison with the heavy ion irradiation results. Corresponding explanations and analysis are discussed.

CMOS Design of Ternary Arithmetic Devices Wu Xunwei Dept.of Electronic Engineering,Hangzhou University,Hangzhou 310028F.P rosser Dept.of Computer Science,Indiana University,U.S.A.

This paper presents CMOS circuit designs of a ternary adder and a ternary multiplier,formulated using transmission function theory.Binary carry signals appearing in these designs allow conventional look-ahead carry techniques to be used.Compared with previous similar designs,the circuits proposed in this paper have advantages such as low dissipation,low output impedance,and simplicity of construction.

Study of latch-up immunization in bulk CMOS integrated circuits exposed to transient ionizing radiation

This paper presents experimental results of transient gamma irradiation effects on two kinds of circuits.One is a two-stage circuit consisting of a bipolar power device L7805CV and a bulk complementary metal-oxide-semiconductor(CMOS) device IDT6116,the other is a two-stage circuit consisting of a bipolar power device L7805CV and the equivalent circuit of the parasitic P-N-P-N structure in bulk CMOS devices.The results show that the L7805CV's output interruption after transient irradiation can prevent latch-up from occurring on the second stage circuit.The demanded minimum interruption duration to avoid latch-up varies with dose rate,and this is confirmed by the experimental results.

Structure design and film process optimization for metal-gate stress in 20 nm nMOS devices

The optimizations to metal gate structure and film process were extensively investigated for great metalgate stress（MGS） in 20 nm high-k/metal-gate-last（HKVMG-last） nMOS devices.The characteristics of advanced MGS technologies on device performances were studied through a process and device simulation by TCAD tools. The metal gate electrode with different stress values（0 to—6 GPa） was implemented in the device simulation along with other traditional process-induced-strain（PIS） technologies like e-SiC and nitride capping layer.The MGS demonstrated a great enhancing effect on channel carriers transporting in the device as device pitch scaling down.In addition,the novel structure for a tilted gate electrode was proposed and relationships between the tilt angle and channel stress were investigated.Also with a new method of fully stressed replacement metal gate（FSRMG） and using plane-shape-HfO to substitute U-shape-HfO,the effect of MGS was improved.For greater film stress in the metal gate,the process conditions for physical vapor deposition（PVD） TiN-x- were optimized.The maximum compressive stress of—6.5 GPa TiN_x was achieved with thinner film and greater RF power as well as about 6 sccm N ratio.

CMOS implementation of a low-power BPSK demodulator for wireless implantable neural command transmission

A new BPSK demodulator was presented.By using a clock multiplier with very simple circuit structure to replace the analog multiplier in the traditional BPSK demodulator,the circuit structure of the demodulator became simpler and hence its power consumption became lower.Simpler structure and lower power will make the designed demodulator more suitable for use in an internal single chip design for a wireless implantable neural recording system.The proposed BPSK demodulator was implemented by Global Foundries 0.35μm CMOS technology with a 3.3 V power supply.The designed chip area is only 0.07 mm;and the power consumption is 0.5 mW.The test results show that it can work correctly.