Total ionizing dose effect modeling method for CMOS digital-integrated circuit

Simulating the total ionizing dose(TID)of an electrical system using transistor-level models can be difficult and expensive,particularly for digital-integrated circuits(ICs).In this study,a method for modeling TID effects in complementary metaloxide semiconductor(CMOS)digital ICs based on the input/output buffer information specification(IBIS)was proposed.The digital IC was first divided into three parts based on its internal structure:the input buffer,output buffer,and functional area.Each of these three parts was separately modeled.Using the IBIS model,the transistor V-I characteristic curves of the buffers were processed,and the physical parameters were extracted and modeled using VHDL-AMS.In the functional area,logic functions were modeled in VHDL according to the data sheet.A golden digital IC model was developed by combining the input buffer,output buffer,and functional area models.Furthermore,the golden ratio was reconstructed based on TID experimental data,enabling the assessment of TID effects on the threshold voltage,carrier mobility,and time series of the digital IC.TID experiments were conducted using a CMOS non-inverting multiplexer,NC7SZ157,and the results were compared with the simulation results,which showed that the relative errors were less than 2%at each dose point.This confirms the practicality and accuracy of the proposed modeling method.The TID effect model for digital ICs developed using this modeling technique includes both the logical function of the IC and changes in electrical properties and functional degradation impacted by TID,which has potential applications in the design of radiation-hardening tolerance in digital ICs.

Study on Si-SiGe Three-Dimensional CMOS Integrated Circuits

Based on the physical characteristics of SiGe material,a new three-dimensional （3D） CMOS IC structure is proposed,in which the first device layer is made of Si material for nMOS devices and the second device layer is made of Six Ge1- x material for pMOS. The intrinsic performance of ICs with the new structure is then limited by Si nMOS.The electrical characteristics of a Si-SiGe 3D CMOS device and inverter are all simulated and analyzed by MEDICI. The simulation results indicate that the Si-SiGe 3D CMOS ICs are faster than the Si-Si 3D CMOS ICs. The delay time of the 3D Si-SiGe CMOS inverter is 2-3ps,which is shorter than that of the 3D Si-Si CMOS inverter.

高速数字化三维集成式CCD-CMOS图像传感器

为了解决CCD与CMOS工艺兼容性低、互连集成制作难度大,以及芯片间接口匹配和高性能兼备等问题,对CCD器件拓扑结构与像元、CMOS读出电路、三维异质互连集成及高密度引脚封装等技术进行研究,提出了一种1024×256阵列规模的集成式CCD-CMOS图像传感器。该器件实现了CCD信号的高精度数字化处理、高速输出及多芯粒的技术融合,填补了国内CCDCMOS三维集成技术空白。测试结果表明:集成CCD-CMOS器件的光响应和成像功能正常,双边成像效果良好,图像无黑条和坏列,互连连通率(99.9%)满足三维集成要求,实现了集成式探测器件的大满阱高灵敏度成像(满阱电子数达165.28ke^(-)、峰值量子效率达86.1%)、高精度数字化(12bit)和高速输出(行频率达100.85kHz),满足集成化、数字化、小型化的多光谱探测成像系统要求。

星敏感器CMOS电路板靶面自动装调系统

CMOS电路板靶面是星敏感器结构中的关键部分,其安装姿态影响离焦距离的准确性,进而影响星敏感器成像性能。因此,靶面的装调是确保星敏感器成像质量的重要环节。当前,靶面装调主要依靠人工装调完成,存在装调精度低、产品一致性差、周期长等问题,导致产品的良品率较低。为此,研制了一台星敏感器CMOS电路板靶面自动装调设备。采取非接触式测量方式,集成测量模组与微动平台完成CMOS靶面与基准面的相对位姿测量,解决由星敏感器特殊结构造成的狭小空间内高精度测量难题。设计调整机构实现零件任意角度翻转,消除测量方向与装配方向不一致造成系统结构布置复杂的影响。最后,对测量系统进行精度分析,采用局部枚举法开发了调整垫片研磨量算法,解决由平面姿态单一已知量反求多垫片研磨量的欠定问题。实验结果表明:该系统可实现靶面自动装调功能,测量系统的重复性为1.6′,满足技术指标要求。

超快四分幅CMOS电路设计与仿真

用于惯性约束聚变诊断的传统微通道板(microchannel plate,MCP)选通分幅相机存在体积大、非单视线成像等问题,可用时间分辨率为百皮秒的CMOS芯片代替MCP变像管,将分幅相机芯片化并实现单视线成像。提出了具有8×8×4像素阵列的单视线四分幅超快成像CMOS电路,并对其性能进行了模拟仿真。基于0.18μm标准CMOS工艺、5晶体管(5T)像素单元结构,设计了四分幅像素单元电路、电压控制延迟器、时钟树以及行列选通电路等。对CMOS电路像素信号进行选通输出并分析,仿真结果表明该CMOS电路可实现单次四分幅成像,每幅图像的时间分辨率为100 ps,相邻两幅图像之间的时间间隔为300 ps,四幅图像像素信号均匀性优于90%。

用于射频能量收集的低阈值CMOS整流电路设计

基于TSMC 180 nm工艺,设计了一款高效率低阈值整流电路。在传统差分输入交叉耦合整流电路的基础上,提出源极与衬底之间增加双PMOS对称辅助晶体管配合缓冲电容的改进结构,对整流晶体管进行阈值补偿。有效缓解了MOS管的衬底偏置效应,降低了整流电路的开启阈值电压,针对较低输入信号功率,提高了整流电路的功率转换效率(PCE)。同时将低阈值整流电路三级级联以提高输出电压。测试结果显示,在输入信号功率为-14 dBm@915 MHz时,三级级联低阈值整流电路实现了升压功能,能稳定输出1.2 V电压,峰值PCE约为71.32%。相较于传统结构,该低阈值整流电路更适合用于射频能量收集。

A Slice Analysis-Based Bayesian Inference Dynamic Power Model for CMOS Combinational Circuits

To improve the accuracy and speed in cycle-accurate power estimation, this paper uses multiple dimensional coefficients to build a Bayesian inference dynamic power model. By analyzing the power distribution and internal node state, we find the deficiency of only using port information. Then, we define the gate level number computing method and the concept of slice, and propose using slice analysis to distill switching density as coefficients in a special circuit stage and participate in Bayesian inference with port information. Experiments show that this method can reduce the power-per-cycle estimation error by 21.9% and the root mean square error by 25.0% compared with the original model, and maintain a 700 ＋ speedup compared with the existing gate-level power analysis technique.

CMOS图像传感器辐射敏感参数测试电路设计及试验验证

以航天领域广泛应用的CMV4000型CMOS图像传感器(CIS)为研究对象,通过开展CIS辐射敏感参数测试电路设计,将CIS辐照电路板与测试电路板中FPGA数据采集及传输板分离,辐照电路板与测试电路板通过接插口通信,从而实现开展辐照试验时对FPGA数据采集部分进行辐射屏蔽防护,避免FPGA数据采集板受到辐射影响。开展了CIS测试电路中的电源模块、数据采集、存储模块、外围电路等设计及PCB版图的布局布线设计。采用VerilogHDL硬件描述语言对各个功能模块进行驱动时序设计,实现CIS辐射敏感参数测试功能。通过开展CMV4000型CIS ^(60)Coγ射线辐照试验,分析了平均暗信号、暗信号非均匀性、暗信号分布等辐射敏感参数随总剂量增大的退化规律,验证了CIS辐射敏感参数测试系统的可靠性。

4H-SiC CMOS高温集成电路设计与制造

设计、制造并测试了基于碳化硅材料的横向MOSFET器件和CMOS电路。常温时,N型和P型MOSFET在片测试的阈值电压分别约为5.4 V和-6.3 V;温度达到300℃时,N型和P型MOSFET的阈值电压分别为4.3 V和-5.3 V。由N型和P型MOSFET组成的CMOS反相器在常温下输出的上升时间为1.44μs,下降时间为2.17μs,且在300℃高温条件下仍可正常工作。由CMOS反相器级联成的环形振荡器在常温下的测试工作频率为147 kHz,在高温下也可正常工作。

5G毫米波反向阵极简构架与CMOS芯片实现

该文首次报道了一种极简构架的5G毫米波反向阵设计原理及其CMOS芯片实现技术。该毫米波反向阵极简构架,利用次谐波混频器提供相位共轭和阵列反向功能,无需移相电路及波束控制系统,便可实现波束自动回溯移动通信功能。该文采用国产0.18μm CMOS工艺研制了5G毫米波反向阵芯片,包括发射前端、接收前端及跟踪锁相环等核心模块,其中发射及接收前端芯片采用次谐波混频及跨导增强等技术,分别实现了19.5 d B和18.7 d B的实测转换增益。所实现的跟踪锁相环芯片具备双模工作优势,可根据不同参考信号支持幅度调制及相位调制,实测输出信号相噪优于–125 dBc/Hz@100 kHz。该文给出的测试结果验证了所提5G毫米波反向阵通信架构及其CMOS芯片实现的可行性,从而为5G/6G毫米波通信探索了一种架构极简、成本极低、拓展性强的新方案。

Bias Current Compensation Method with 41.4% Standard Deviation Reduction to MOSFET Transconductance in CMOS Circuits

A simple and successful method for the stability enhancement of integrated circuits is presented. When the process parameters, temperature, and supply voltage are changed, according to the simulation results, this method yields a standard deviation of the transconductance of MOSFETs that is 41.4% less than in the uncompensated case. This method can be used in CMOS LC oscillator design.

一种紧凑的射频CMOS放大器LC输出匹配电路

提出了一种紧凑的射频互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)放大器LC输出匹配电路,利用放大器漏极偏置电感、输出端隔直电容与放大器输出端并联电感电容形成高阶LC谐振网络,可在占用较小芯片面积的条件下实现较传统L型匹配电路更宽频率范围的输出阻抗匹配。推导了该LC输出匹配电路元件值的计算式,并根据提出的设计方法,采用65 nm CMOS工艺设计了一款K频段放大器,其输出匹配电路尺寸仅98μm×150μm。仿真结果表明,在16.5~22.1 GHz频率范围内放大器的S 22<-10 dB,阻抗匹配带宽相比L型匹配电路增加166%。放大器实测S参数和仿真结果相符,验证了该LC匹配电路可实现紧凑的宽带阻抗匹配。

DESIGN OF TERNARY CURRENT-MODE CMOS CIRCUITS BASED ON SWITCH-SIGNAL THEORY

By applying switch-signal theory, the interaction between MOS transmission switch-ing transistor and current signal in current-mode CMOS circuits is analyzed, and the theory oftransmission current-switches which is suitable to current-mode CMOS circuits is proposed. Thecircuits, such as ternary full-adder etc., designed by using this theory have simpler circuit struc-tures and correct logic functions. It is confirmed that this theory is efficient in guiding the logicdesign of current-mode CMOS circuits at switch level.

面向超大面阵CMOS图像传感器的全局斜坡一致性校正方法

针对大面阵CMOS图像传感器(CIS)中存在的斜坡信号不一致性问题,该文提出一种用于CMOS图像传感器的斜坡一致性校正方法。该误差校正方法基于误差存储和电平移位思想,在列级读出电路中引入用于存储各列斜坡不一致性误差的存储电容,根据存储的斜坡不一致性误差对各列的斜坡信号进行电平移位,确保斜坡信号的一致性。该文基于55 nm 1P4M CMOS工艺对提出的斜坡一致性校正方法完成了详细电路设计和全面仿真验证。在斜坡信号电压范围为1.4 V,斜坡信号斜率为71.908 V/ms,像素面阵规模为8 192(H)×8 192(V),单个像素尺寸为10μm的设计条件下,该文提出的校正方法将斜坡不一致性误差从7.89 mV降低至36.8μV。斜坡信号的微分非线性(DNL)为+0.001 3/–0.004 LSB,积分非线性(INL)为+0.045/–0.02 LSB,列级固定模式噪声(CFPN)从1.9%降低到0.01%。该文提出的斜坡一致性校正方法在保证斜坡信号高线性度,不显著增加芯片面积和不引入额外功耗的基础上,斜坡不一致性误差降低了99.53%,为高精度CMOS图像传感器的设计提供了一定的理论支撑。

一种基于0.18 um工艺的高增益CMOS运算放大器

高增益CMOS运算放大器在集成电路设计中扮演着重要角色。CMOS运算放大器具有高增益特性,能够放大微弱的信号,并在电路中提供稳定的放大功能。提出了一种新型高增益CMOS运算放大器的设计方案,由4个三端NMOS管和4个三端PMOS管共同构成,通过优化电路结构和参数配置,结合了负反馈和级联放大器的优势,实现了较高的增益和性能指标。该运算放大器采用0.18 um CMOS工艺设计,仿真结果表明,在电压为1.8 V,负载电容为60 pF的环境下,该运算放大器的开环直流增益为81dB,增益带宽为110 M H z,相位裕度为72.9°,电源抑制比110 dB,电源总功耗仅为55 uW。大大提升了运放的增益,降低了电路的功耗并节省了面积。

基于BGR芯片设计的CMOS集成电路教学新范式

针对集成电路专业实验教学中软件使用难度高以及教学模式单一的问题,结合专业培养方案对课程知识与能力的要求,提出一种基于BGR芯片设计的CMOS集成电路教学新范式。该文采用调研分析、调查问卷、理论+实践、系统评估等方法,培养学生实验技能、设计思想、EDA方法和分析方法,从而提高学生在模拟芯片设计方面的实践能力和创新意识。教学实践表明,该教学模式在集成电路人才培养实践教学中取得了良好的教学效果。

A single-ended wideband reconfigurable receiver front-end for multi-mode multi-standard applications in 0.18μm CMOS

This paper presents a reconfigurable RF front-end for multi-mode multi-standard(MMMS) applications. The designed RF front-end is fabricated in 0.18 μm RF CMOS technology. The low noise characteristic is achieved by the noise canceling technique while the bandwidth is enhanced by gate inductive peaking technique. Measurement results show that, while the input frequency ranges from 100 MHz to 2.9 GHz, the proposed reconfigurable RF front-end achieves a controllable voltage conversion gain(VCG) from 18 dB to 39 dB. The measured maximum input third intercept point(IIP3) is-4.9 dBm and the minimum noise figure(NF) is 4.6 dB. The consumed current ranges from 16 mA to 26.5 mA from a 1.8 V supply voltage. The chip occupies an area of 1.17 mm^2 including pads.

New Design Methodologies for High Speed Low-Voltage 1-Bit CMOS Full Adder Circuits

New methodologies for l-Bit XOR-XNOR full- adder circuits are proposed to improve the speed and power as these circuits are basic building blocks for ALU circuit implementation. This paper presents comparative study of high-speed, low-power and low voltage full adder circuits. Simulation results illustrate the superiority of the proposed adder circuit against the conventional complementary metal-oxide-semiconductor （CMOS）, complementary pass-transistor logic （CPL）, TG, and Hybrid adder circuits in terms of delay, power and power delay product （PDP）. Simulation results reveal that the proposed circuit exhibits lower PDP and is more power efficient and faster when compared with the best available 1-bit full adder circuits. The design is implemented on UMC 0.18 μm process models in Cadence Virtuoso Schematic Composer at 1.8 V single ended supply voltage and simulations are carried out on Spectre S.

基于0.18μm CMOS工艺的低功耗采样保持电路

基于0.18μm CMOS工艺设计了一款用于ADC前端的采样保持电路,电路采用输入缓冲器-采样开关-输出缓冲器三级结构实现。为提高采样保持电路的保持平稳度,设计了信号馈通和时钟馈通消除结构。为改善频率响应,设计了无源负反馈结构并研究了器件参数对电路性能的影响。仿真结果表明,该馈通消除结构能够提升保持阶段的平稳度,负反馈可将增益提升36 dB。该电路在800 MS/s采样率、122.6 MHz正弦波输入条件下,增益为0 dB,3 dB带宽为1 GHz,信号失真比为48 dB,有效位数为7.7 bit。最终版图面积为202μm×195μm,功耗为37.22 mW,实现了低功耗的设计目标。

A Comparative Study of Majority/Minority Logic Circuit Synthesis Methods for Post-CMOS Nanotechnologies

The physical limitations of complementary metal-oxide semiconductor?(CMOS) technology have led many researchers to consider other alternative technologies. Quantum-dot cellular automate (QCA), single electron tunneling (SET), tunneling phase logic (TPL), spintronic devices, etc., are some of the nanotechnologies that are being considered as possible replacements for CMOS. In these nanotechnologies, the basic logic units used to implement circuits are majority and/or minority gates. Several majority/minority logic circuit synthesis methods have been proposed. In this paper, we give a comparative study of the existing majority/minority logic circuit synthesis methods that are capable of synthesizing multi-input multi-output Boolean functions. Each of these methods is discussed in detail. The optimization priorities given to different factors such as gates, levels, inverters, etc., vary with technologies. Based on these optimization factors, the results obtained from different synthesis methods are compared. The paper also analyzes the optimization capabilities of different methods and discusses directions for future research in the synthesis of majority/minority logic networks.