CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in t...CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in the charge transfer path,which reduces the charge transfer efficiency and image quality.Until now,scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition.However,the existing models have thus far ignored the charge transfer limitation due to Si/SiO_(2)interface state traps in the transfer gate channel,particularly under low illumination.Therefore,this paper proposes,for the first time,an analytical model for quantifying the incomplete charge transfer caused by Si/SiO_(2)interface state traps in the transfer gate channel under low illumination.This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution,exponential distribution and measured distribution.The model was verified with technology computer-aided design simulations,and the results showed that the simulation results exhibit the consistency with the proposed model.展开更多
A novel CMOS image sensor(CIS) pinned photodiode(PPD) pixel, named as O-T pixel, is proposed and investigated by TCAD simulations. Compared with the conventional PPD pixel, the proposed pixel features the overlapping ...A novel CMOS image sensor(CIS) pinned photodiode(PPD) pixel, named as O-T pixel, is proposed and investigated by TCAD simulations. Compared with the conventional PPD pixel, the proposed pixel features the overlapping gate(OG)and the temporary storage diffusing(TSD) region, based on which the several-nanosecond-level charge transfer could be achieved and the complete charge transfer from the PPD to the floating node(FD) could be realized. And systematic analyses of the influence of the doping conditions of the proposed processes, the OG length, and the photodiode length on the transfer performances of the proposed pixel are conducted. Optimized simulation results show that the total charge transfer time could reach about 5.862 ns from the photodiode to the sensed node and the corresponding charge transfer efficiency could reach as high as 99.995% in the proposed pixel with 10 μm long photodiode and 2.22 μm long OG. These results demonstrate a great potential of the proposed pixel in high-speed applications.展开更多
In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metal...In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 gm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.展开更多
The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random t...The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result,the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated,and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures.展开更多
High linearity and low noise column readout chain are two key factors in CMOS image sensor.However,offset mismatch and charge sharing always exist in the conventional column wise readout implementation,even adopting t...High linearity and low noise column readout chain are two key factors in CMOS image sensor.However,offset mismatch and charge sharing always exist in the conventional column wise readout implementation,even adopting the technology of correlated double sample.A simple column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor is proposed in this paper.Based on the bottom plate sampling and fixed common level method,this novel design can avoid the offset nonuniformity between the two buffers.Also,the single buffer and switched capacitor technique can effectively suppress the charge sharing caused by the varied operating point.The proposed approach is experimentally verified in a 1024×1024 prototype chip designed and fabricated in 55 nm low power CMOS process.The measurement results show that the linear range is extended by 20%,the readout noise of bright and dark fields is reduced by 40%and 30%respectively,and the improved photo response nonuniformity is up to 1.16%.Finally,a raw sample image taken by the prototype sensor shows the excellent practical performance.展开更多
This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer...This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD.Dual-CDS is used to reduce random noise and the nonuniformity between columns.Dual-mode counting method is proposed to improve circuit robustness.A prototype sensor was fabricated using a 0.11μm CMOS process.Measurement results show that the lag of the five-finger shaped pixel is reduced by 80%compared with the conventional rectangular pixel,the chip power consumption is only 36 mW,the dynamic range is 67.3 dB,the random noise is only 1.55 e^(-)_(rms),and the figure-of-merit is only 1.98 e^(-)·nJ,thus realizing low-power and high-quality imaging.展开更多
To improve the full well capacity (FWC) of a small size backside illuminated (BSI) CMOS image sensor (CIS), the effect of photodiode capacitance (Cpo) on FWC is studied, and a reformed pinned photodiode (PPD...To improve the full well capacity (FWC) of a small size backside illuminated (BSI) CMOS image sensor (CIS), the effect of photodiode capacitance (Cpo) on FWC is studied, and a reformed pinned photodiode (PPD) structure is proposed. Two procedures are implemented for the optimization. The first is to form a varying doping concentration and depth stretched new N region, which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region. The FWC of this structure is increased by extending the side wall junctions in the substrate. Secondly, in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region. This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period. The simulation results show that the FWC can be improved from 1289e- to 6390e-, and this improvement does not sacrifice any image lag performance. Additionally, quantum efficiency (QE) is enhanced in the full wavelength range, especially 6.3% at 520 nm wavelength. This technique can not only be used in such BSI structures, but also adopted in an FSI pixel with any photodiode-type readout scheme.展开更多
Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type ...Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10^12 cm^-2,an implant tilt of -2°,a transfer gate channel doping dose of 3.0×10^12 cm^-2 and an operation voltage of 3.4 V.The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.展开更多
A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and e...A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.展开更多
Abs A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size. Based on the emission current theory, a qualitative photoresponse model is established to th...Abs A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size. Based on the emission current theory, a qualitative photoresponse model is established to the preliminary prediction. Further analysis of noise for incomplete charge transfer predicts the noise variation. The test pixels were fabricated in a specialized 0.18 #m CMOS image sensor process and two different processes of buried N layer implantation are compared. The trend prediction corresponds with the test results, especially as it can distinguish an unobvious incomplete charge transfer. The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.展开更多
This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodio...This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 x 64 pixels was designed and implemented in the 0.18 #m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.展开更多
A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic bef...A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to singleevent latch up for LET up to110 Me V cm^2/mg.展开更多
The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardl...The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.展开更多
This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS ci...This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.展开更多
A 10-bit ratio-independent switch-capacitor(SC) cyclic analog-to-digital converter(ADC) with offset cancelingforaCMOSimagesensorispresented.TheproposedADCcompletesanN-bitconversionin1.5N clock cycles with one oper...A 10-bit ratio-independent switch-capacitor(SC) cyclic analog-to-digital converter(ADC) with offset cancelingforaCMOSimagesensorispresented.TheproposedADCcompletesanN-bitconversionin1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversioncharacteristicoftheproposedcyclicADCisinherentlyinsensitivebothtocapacitorratioandtoamplifieroffset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18- m one-poly four-metal CMOS technology.The measured results indicate that the ADC has a signal-to-noise and distortion ratio(SNDR) of 53.6 dB and a DNL of C0:12/0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 W with a 1.8 V supply, and its area is0.030.8 mm2.展开更多
In this paper, a new photodetector, bipolar junction photogate transistor (BJPG), is proposed for CMOS imagers. Due to an injection p+n junction introduced, the photo-charges drift through the p+n junction by the appl...In this paper, a new photodetector, bipolar junction photogate transistor (BJPG), is proposed for CMOS imagers. Due to an injection p+n junction introduced, the photo-charges drift through the p+n junction by the applied electronic field, and on the other hand, the p+n junction injects the carriers into the channel to carry the photo-charges. Therefore this device can increase the readout rate of the pixel signal charges and the photoelectron transferring efficiency. Using this new device, a new type of logarithmic pixel circuit is obtained with a wide dynamic range which makes photo-detector more suitable for imaging the naturally illuminated scenes. The simulations show that the photo current density of BJPG increases logarithmically with the incident light power due to the introduced injection p+n junction. The noise characteristics of BJPG are analyzed in detail and a new gate-induced noise is proposed. Based on the established numerical analytical model of noise, the power spectrum density curves are simulated.展开更多
Changes of the average brightness and non-uniformity of dark output images,and quality of pictures captured under natural lighting for the color CMOS digital image sensorsirradiated at different electron doses have be...Changes of the average brightness and non-uniformity of dark output images,and quality of pictures captured under natural lighting for the color CMOS digital image sensorsirradiated at different electron doses have been studied in comparison to those from theγ-irradiated sensors. For the electron-irradiated sensors, the non-uniformity increases obviouslyand a small bright region on the dark image appears at the dose of 0.4 kGy. The average brightnessincreases at 0.4 kGy, increases sharply at 0.5 kGy. The picture is very blurry only at 0.6 kGy,showing the sensor undergoes severe performance degradation. Electron radiation damage is much moresevere than γ radiation damage for the CMOS image sensors. A possible explanation is presented inthis paper.展开更多
The 9 and 12 MeV proton irradiations of the Chinese CMOS Image Sensor in the fluence range from 1× 10^9 to 4×10^10 cm^-2 and 1 × 10^9 to 2×10^12 cm^-2 have been carried out respectively. The color ...The 9 and 12 MeV proton irradiations of the Chinese CMOS Image Sensor in the fluence range from 1× 10^9 to 4×10^10 cm^-2 and 1 × 10^9 to 2×10^12 cm^-2 have been carried out respectively. The color pictures and dark output images are captured, and the average brightness of dark output images is calculated. The anti-irradiation fluence thresholds for 9 and 12 MeV protons are about 4×10^l0 and 2×10^12 cm^-2, respectively. These can be explained by the change of the concentrations of irradiation-induced electron-hole pairs and vacancies in the various layers of CMOS image sensor calculated by the TRIM simulation program.展开更多
A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18μm CI...A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination.展开更多
A wide-dynamic-range CMOS image sensor(CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion(FD) of a five-transistor active pixel is proposed.With optimized pixel opera...A wide-dynamic-range CMOS image sensor(CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion(FD) of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second(fps).The proposed CMOS image sensor meets the demands of applications in security surveillance systems.展开更多
基金supported by the National Natural Science Foundation of China(62171172).
文摘CMOS image sensors produced by the existing CMOS manufacturing process usually have difficulty achieving complete charge transfer owing to the introduction of potential barriers or Si/SiO_(2)interface state traps in the charge transfer path,which reduces the charge transfer efficiency and image quality.Until now,scholars have only considered mechanisms that limit charge transfer from the perspectives of potential barriers and spill back effect under high illumination condition.However,the existing models have thus far ignored the charge transfer limitation due to Si/SiO_(2)interface state traps in the transfer gate channel,particularly under low illumination.Therefore,this paper proposes,for the first time,an analytical model for quantifying the incomplete charge transfer caused by Si/SiO_(2)interface state traps in the transfer gate channel under low illumination.This model can predict the variation rules of the number of untransferred charges and charge transfer efficiency when the trap energy level follows Gaussian distribution,exponential distribution and measured distribution.The model was verified with technology computer-aided design simulations,and the results showed that the simulation results exhibit the consistency with the proposed model.
基金Project supported by the National Natural Science Foundation of China(Grant No.61574112)。
文摘A novel CMOS image sensor(CIS) pinned photodiode(PPD) pixel, named as O-T pixel, is proposed and investigated by TCAD simulations. Compared with the conventional PPD pixel, the proposed pixel features the overlapping gate(OG)and the temporary storage diffusing(TSD) region, based on which the several-nanosecond-level charge transfer could be achieved and the complete charge transfer from the PPD to the floating node(FD) could be realized. And systematic analyses of the influence of the doping conditions of the proposed processes, the OG length, and the photodiode length on the transfer performances of the proposed pixel are conducted. Optimized simulation results show that the total charge transfer time could reach about 5.862 ns from the photodiode to the sensed node and the corresponding charge transfer efficiency could reach as high as 99.995% in the proposed pixel with 10 μm long photodiode and 2.22 μm long OG. These results demonstrate a great potential of the proposed pixel in high-speed applications.
基金Project supported by the Key Program of the National Natural Science Foundation of China (Grant No. 61036004)the Shenzhen Science & Technology Foundation, China (Grant No. CXB201005250031A)+1 种基金the Fundamental Research Project of Shenzhen Science & Technology Foundation, China (Grant No. JC201005280670A)the International Collaboration Project of Shenzhen Science & Technology Foundation, China (Grant No. ZYA2010006030006A)
文摘In this paper we report on a study of the CMOS image sensor detection of DNA based on self-assembled nano- metallic particles, which are selectively deposited on the surface of the passive image sensor. The nano-metallic particles effectively block the optical radiation in the visible spectrum of ordinary light source. When such a technical method is applied to DNA detection, the requirement for a special UV light source in the most popular fluorescence is eliminated. The DNA detection methodology is tested on a CMOS sensor chip fabricated using a standard 0.5 gm CMOS process. It is demonstrated that the approach is highly selective to detecting even a signal-base mismatched DNA target with an extremely-low-concentration DNA sample down to 10 pM under an ordinary light source.
基金Project supported by the National Natural Science Foundation of China(Grant Nos.61372156 and 61405053)the Natural Science Foundation of Zhejiang Province of China(Grant No.LZ13F04001)
文摘The random telegraph signal noise in the pixel source follower MOSFET is the principle component of the noise in the CMOS image sensor under low light. In this paper, the physical and statistical model of the random telegraph signal noise in the pixel source follower based on the binomial distribution is set up. The number of electrons captured or released by the oxide traps in the unit time is described as the random variables which obey the binomial distribution. As a result,the output states and the corresponding probabilities of the first and the second samples of the correlated double sampling circuit are acquired. The standard deviation of the output states after the correlated double sampling circuit can be obtained accordingly. In the simulation section, one hundred thousand samples of the source follower MOSFET have been simulated,and the simulation results show that the proposed model has the similar statistical characteristics with the existing models under the effect of the channel length and the density of the oxide trap. Moreover, the noise histogram of the proposed model has been evaluated at different environmental temperatures.
基金supported by Shaanxi Education Department (No. 19JC029)
文摘High linearity and low noise column readout chain are two key factors in CMOS image sensor.However,offset mismatch and charge sharing always exist in the conventional column wise readout implementation,even adopting the technology of correlated double sample.A simple column readout circuit with improved offset mismatch and charge sharing for CMOS image sensor is proposed in this paper.Based on the bottom plate sampling and fixed common level method,this novel design can avoid the offset nonuniformity between the two buffers.Also,the single buffer and switched capacitor technique can effectively suppress the charge sharing caused by the varied operating point.The proposed approach is experimentally verified in a 1024×1024 prototype chip designed and fabricated in 55 nm low power CMOS process.The measurement results show that the linear range is extended by 20%,the readout noise of bright and dark fields is reduced by 40%and 30%respectively,and the improved photo response nonuniformity is up to 1.16%.Finally,a raw sample image taken by the prototype sensor shows the excellent practical performance.
基金supported by the National Key R&D Program of China(2019YFB2204304).
文摘This paper presents a low-power high-quality CMOS image sensor(CIS)using 1.5 V 4T pinned photodiode(4T-PPD)and dual correlated double sampling(dual-CDS)column-parallel single-slope ADC.A five-finger shaped pixel layer is proposed to solve image lag caused by low-voltage 4T-PPD.Dual-CDS is used to reduce random noise and the nonuniformity between columns.Dual-mode counting method is proposed to improve circuit robustness.A prototype sensor was fabricated using a 0.11μm CMOS process.Measurement results show that the lag of the five-finger shaped pixel is reduced by 80%compared with the conventional rectangular pixel,the chip power consumption is only 36 mW,the dynamic range is 67.3 dB,the random noise is only 1.55 e^(-)_(rms),and the figure-of-merit is only 1.98 e^(-)·nJ,thus realizing low-power and high-quality imaging.
基金Project supported by the National Natural Science Foundation of China(Nos.61036004,60976030)
文摘To improve the full well capacity (FWC) of a small size backside illuminated (BSI) CMOS image sensor (CIS), the effect of photodiode capacitance (Cpo) on FWC is studied, and a reformed pinned photodiode (PPD) structure is proposed. Two procedures are implemented for the optimization. The first is to form a varying doping concentration and depth stretched new N region, which is implemented by an additional higher-energy and lower-dose N type implant beneath the original N region. The FWC of this structure is increased by extending the side wall junctions in the substrate. Secondly, in order to help the enlarged well capacity achieve full depletion, two step P-type implants with different implant energies are introduced to form a P-type insertion region in the interior of the stretched N region. This vertical inserted P region guarantees that the proposed new PD structure achieves full depletion in the reset period. The simulation results show that the FWC can be improved from 1289e- to 6390e-, and this improvement does not sacrifice any image lag performance. Additionally, quantum efficiency (QE) is enhanced in the full wavelength range, especially 6.3% at 520 nm wavelength. This technique can not only be used in such BSI structures, but also adopted in an FSI pixel with any photodiode-type readout scheme.
基金supported by the National Natural Science Foundation of China(Nos.60806010,60976030)the Tianjin Innovation Special Funds for science and Technology,China(No.05FZZDGX00200)
文摘Pixel image lag in a 4-T CMOS image sensor is analyzed and simulated in a two-dimensional model.Strategies of reducing image lag are discussed from transfer gate channel threshold voltage doping adjustment,PPD N-type doping dose/implant tilt adjustment and transfer gate operation voltage adjustment for signal electron transfer.With the computer analysis tool ISE-TCAD,simulation results show that minimum image lag can be obtained at a pinned photodiode n-type doping dose of 7.0×10^12 cm^-2,an implant tilt of -2°,a transfer gate channel doping dose of 3.0×10^12 cm^-2 and an operation voltage of 3.4 V.The conclusions of this theoretical analysis can be a guideline for pixel design to improve the performance of 4-T CMOS image sensors.
基金supported by the National Natural Science Foundation of China (No. 60576025)the Tianjin Innovation Special Funds forScience and Technology, China (No. 05FZZDGX00200).
文摘A low power linear stepping digital programming gain amplifier (PGA) is designed for CMOS image sensors. The PGA consists of three stages with gain range from one to nine, The gain is divided into four regions and each range has 128 linear steps. Power consumption of the PGA is saved by good tradeoff between variation of amplifier feedback coefficient, pipeline stages and gain regions. With thermometer-binary mixed coding and linear pipeline gain stepping, the load capacitance keeps constant when the gain of one stage is changed. The PGA is designed in the SMIC 0.18 μm process. Simulation results show that the power consumption is 3.2 mW with 10 bit resolution and 10 MSPS sampling rate. The PGA has been embedded in a 0.3 megapixel CMOS image sensors and fabricated successfully.
基金supported by the National Natural Science Foundation of China(Nos.61036004,61076024)
文摘Abs A method to judge complete charger transfer is proposed for a four-transistor CMOS image sensor with a large pixel size. Based on the emission current theory, a qualitative photoresponse model is established to the preliminary prediction. Further analysis of noise for incomplete charge transfer predicts the noise variation. The test pixels were fabricated in a specialized 0.18 #m CMOS image sensor process and two different processes of buried N layer implantation are compared. The trend prediction corresponds with the test results, especially as it can distinguish an unobvious incomplete charge transfer. The method helps us judge whether the charge transfer time satisfies the requirements of the readout circuit for the given process especially for pixels of a large size.
基金supported by the National Natural Science Foundation of China(No.61234003)the Special Funds for Major State Basic Research Project of China(No.2011CB932902)
文摘This paper proposes pixel process techniques to reduce the charge transfer time in high speed CMOS image sensors. These techniques increase the lateral conductivity of the photo-generated carriers in a pinned photodiode (PPD) and the voltage difference between the PPD and the floating diffusion (FD) node by controlling and optimizing the N doping concentration in the PPD and the threshold voltage of the reset transistor, respectively. The techniques shorten the charge transfer time from the PPD diode to the FD node effectively. The proposed process techniques do not need extra masks and do not cause harm to the fill factor. A sub array of 32 x 64 pixels was designed and implemented in the 0.18 #m CIS process with five implantation conditions splitting the N region in the PPD. The simulation and measured results demonstrate that the charge transfer time can be decreased by using the proposed techniques. Comparing the charge transfer time of the pixel with the different implantation conditions of the N region, the charge transfer time of 0.32 μs is achieved and 31% of image lag was reduced by using the proposed process techniques.
文摘A systemic solution for radiation hardened design is presented. Besides, a series of experiments have been carried out on the samples, and then the photoelectric response characteristic and spectral characteristic before and after the experiments have been comprehensively analyzed. The performance of the CMOS image sensor with the radiation hardened design technique realized total-dose resilience up to 300 krad(Si) and resilience to singleevent latch up for LET up to110 Me V cm^2/mg.
基金Project supported by the National Defense Pre-Research Foundation of China(No.51311050301095)
文摘The charge transfer potential barrier (CTPB) formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode (PPD) CMOS image sensors (CIS), and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.
基金supported by the National Natural Science Foundation of China(Nos.60976023,61234003)the Special Funds for Major State Basic Research Project of China(No.2011CB932902)
文摘This paper presents a high-speed column-parallel cyclic analog-to-digital converter(ADC) for a CMOS image sensor.A correlated double sampling(CDS) circuit is integrated in the ADC,which avoids a stand-alone CDS circuit block.An offset cancellation technique is also introduced,which reduces the column fixed-pattern noise(FPN) effectively.One single channel ADC with an area less than 0.02 mm^2 was implemented in a 0.13μm CMOS image sensor process.The resolution of the proposed ADC is 10-bit,and the conversion rate is 1.6 MS/s. The measured differential nonlinearity and integral nonlinearity are 0.89 LSB and 6.2 LSB together with CDS, respectively.The power consumption from 3.3 V supply is only 0.66 mW.An array of 48 10-bit column-parallel cyclic ADCs was integrated into an array of CMOS image sensor pixels.The measured results indicated that the ADC circuit is suitable for high-speed CMOS image sensors.
基金Project supported by the National Natural Science Foundation of China(Nos.61234003,61274021)
文摘A 10-bit ratio-independent switch-capacitor(SC) cyclic analog-to-digital converter(ADC) with offset cancelingforaCMOSimagesensorispresented.TheproposedADCcompletesanN-bitconversionin1.5N clock cycles with one operational amplifier. Combining ratio-independent and polarity swapping techniques, the conversioncharacteristicoftheproposedcyclicADCisinherentlyinsensitivebothtocapacitorratioandtoamplifieroffset voltage. Therefore, the circuit can be realized in a small die area and it is suitable to serve as the column-parallel ADC in CMOS image sensors. A prototype ADC is fabricated in 0.18- m one-poly four-metal CMOS technology.The measured results indicate that the ADC has a signal-to-noise and distortion ratio(SNDR) of 53.6 dB and a DNL of C0:12/0:14 LSB at a conversion rate of 600 kS/s. The standard deviation of the offset variation of the ADC is reduced from 2.5 LSB to 0.5 LSB. Its power dissipation is 250 W with a 1.8 V supply, and its area is0.030.8 mm2.
文摘In this paper, a new photodetector, bipolar junction photogate transistor (BJPG), is proposed for CMOS imagers. Due to an injection p+n junction introduced, the photo-charges drift through the p+n junction by the applied electronic field, and on the other hand, the p+n junction injects the carriers into the channel to carry the photo-charges. Therefore this device can increase the readout rate of the pixel signal charges and the photoelectron transferring efficiency. Using this new device, a new type of logarithmic pixel circuit is obtained with a wide dynamic range which makes photo-detector more suitable for imaging the naturally illuminated scenes. The simulations show that the photo current density of BJPG increases logarithmically with the incident light power due to the introduced injection p+n junction. The noise characteristics of BJPG are analyzed in detail and a new gate-induced noise is proposed. Based on the established numerical analytical model of noise, the power spectrum density curves are simulated.
基金This project is financially supported by the Narional Natural Science Foundation of China(Nos 10375034 and 10075029) and the Basic Research Foundation of Tsinghua University (No. JC2002058).
文摘Changes of the average brightness and non-uniformity of dark output images,and quality of pictures captured under natural lighting for the color CMOS digital image sensorsirradiated at different electron doses have been studied in comparison to those from theγ-irradiated sensors. For the electron-irradiated sensors, the non-uniformity increases obviouslyand a small bright region on the dark image appears at the dose of 0.4 kGy. The average brightnessincreases at 0.4 kGy, increases sharply at 0.5 kGy. The picture is very blurry only at 0.6 kGy,showing the sensor undergoes severe performance degradation. Electron radiation damage is much moresevere than γ radiation damage for the CMOS image sensors. A possible explanation is presented inthis paper.
基金National Natural Science Foundation of China(10375034,10075029)
文摘The 9 and 12 MeV proton irradiations of the Chinese CMOS Image Sensor in the fluence range from 1× 10^9 to 4×10^10 cm^-2 and 1 × 10^9 to 2×10^12 cm^-2 have been carried out respectively. The color pictures and dark output images are captured, and the average brightness of dark output images is calculated. The anti-irradiation fluence thresholds for 9 and 12 MeV protons are about 4×10^l0 and 2×10^12 cm^-2, respectively. These can be explained by the change of the concentrations of irradiation-induced electron-hole pairs and vacancies in the various layers of CMOS image sensor calculated by the TRIM simulation program.
基金Project supported by the National Natural Science Foundation of China(Nos.60806010,60976030)the Research Fund for the Doctoral Program of Higher Education of China(No.200800561111)
文摘A low reset noise CMOS image sensor (CIS) based on column-level feedback reset is proposed. A feedback loop was formed through an amplifier and a switch. A prototype CMOS image sensor was developed with a 0.18μm CIS process. Through matching the noise bandwidth and the bandwidth of the amplifier, with the falling time period of the reset impulse 6μs, experimental results show the reset noise level can experience up to 25 dB reduction. The proposed CMOS image sensor meets the demand of applications in high speed security surveillance systems, especially in low illumination.
基金supported by the National Natural Science Foundation of China(Nos.60806010,60976030)the Tianjin Innovation Special Funds for Science and Technology,China(No.05FZZDGX00200).
文摘A wide-dynamic-range CMOS image sensor(CIS) based on synthesis of a long-time and a short-time exposure signal in the floating diffusion(FD) of a five-transistor active pixel is proposed.With optimized pixel operation,the response curve is compressed and a wide dynamic range image is obtained.A prototype wide-dynamic-range CMOS image sensor was developed with a 0.18μm CIS process.With the double exposure time 2.4 ms and 70 ns,the dynamic range of the proposed sensor is 80 dB with 30 frames per second(fps).The proposed CMOS image sensor meets the demands of applications in security surveillance systems.