The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardl...The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.展开更多
A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is propos...A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise （FPN） reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit （I2C） interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW.展开更多
基金Project supported by the National Defense Pre-Research Foundation of China(No.51311050301095)
文摘The charge transfer potential barrier （CTPB） formed beneath the transfer gate causes a noticeable image lag issue in pinned photodiode （PPD） CMOS image sensors （CIS）, and is difficult to measure straightforwardly since it is embedded inside the device. From an understanding of the CTPB formation mechanism, we report on an alternative method to feasibly measure the CTPB height by performing a linear extrapolation coupled with a horizontal left-shift on the sensor photoresponse curve under the steady-state illumination. The theoretical study was pertbrmed in detail on the principle of the proposed method. Application of the measurements oil a prototype PPD-CIS chip with an array of 160 ×160 pixels is demonstrated. Such a method intends to shine new light oil the guidance for the lag-free and high-speed sensors optimization based on PPD devices.
基金supported by the National"863"Program of China under Grant No.2008AA01Z130
文摘A digital still camera image processing system on a chip, different from the video camera system, is pre- sented for mobile phone to reduce the power consumption and size. A new color interpolation algorithm is proposed to enhance the image quality. The system can also process fixed patten noise （FPN） reduction, color correction, gamma correction, RGB/YUV space transfer, etc. The chip is controlled by sensor regis- ters by inter-integrated circuit （I2C） interface. The voltage for both the front-end analog and the pad cir- cuits is 2.8 V, and the volatge for the image signal processing is 1.8 V. The chip running under the external 13.5-MHz clock has a video data rate of 30 frames/s and the measured power dissipation is about 75 roW.
