Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology....Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology. Two samples have been irradiated un-biased by 23 MeV protons with fluences of 1.43 × 10^11 protons/cm^2 and 2.14 × 10^11 protons/cm-2,respectively, while another sample has been exposed un-biased to 65 krad（Si） ^60Co γ-ray. The influences of radiation on the dark current, fixed-pattern noise under illumination, quantum efficiency, and conversion gain of the samples are investigated. The dark current, which increases drastically, is obtained by the theory based on thermal generation and the trap induced upon the irradiation. Both γ-ray and proton irradiation increase the non-uniformity of the signal, but the nonuniformity induced by protons is even worse. The degradation mechanisms of CMOS APS image sensors are analyzed,especially for the interaction induced by proton displacement damage and total ion dose（TID） damage.展开更多
A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and succ...A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and success-fully taped out with a Chartered 0.35μm process. The pixel pitch is 8μm × 8μm with a fill factor of 57%, the photo-sensitivity is 0.8V/（lux · s） ,and the dynamic range is 50dB. Theoretical analysis and test results indicate that as the process is scaled down, a smaller pixel pitch reduces the sensitivity. A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.展开更多
A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It...A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2 μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.展开更多
A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added...A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64×64 CIS and successfully fabricated with chartered 0.35 μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier.展开更多
A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 4...A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.展开更多
A pinned photodiode complementary metal–oxide–semiconductor transistor（CMOS） active pixel sensor is exposed to ^60Co to evaluate the performance for space applications. The sample is irradiated with a dose rate of...A pinned photodiode complementary metal–oxide–semiconductor transistor（CMOS） active pixel sensor is exposed to ^60Co to evaluate the performance for space applications. The sample is irradiated with a dose rate of 50 rad（SiO2）/s and a total dose of 100 krad（SiO2）, and the photodiode is kept unbiased. The degradation of dark current, full well capacity,and quantum efficiency induced by the total ionizing dose damage effect are investigated. It is found that the dark current increases mainly from the shallow trench isolation（STI） surrounding the pinned photodiode. Further results suggests that the decreasing of full well capacity due to the increase in the density, is induced by the total ionizing dose（TID） effect, of the trap interface, which also leads to the degradation of quantum efficiency at shorter wavelengths.展开更多
A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) ...A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) is used in the chip,which comprises a 256×256 pixel array together with column amplifiers,scan array circuits,series interface,control logic and Analog-Digital Converter (ADC). With the use of smart layout design,fill factor of pixel cell is 43%. Moreover,a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used. The CMOS image sensor chip is implemented based on the 0.35μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.展开更多
基金Project supported the National Natural Science Foundation of China(Grant No.11675259)the West Light Foundation of the Chinese Academy of Sciences(Grant Nos.XBBS201316,2016-QNXZ-B-2,and 2016-QNXZ-B-8)Young Talent Training Project of Science and Technology,Xinjiang,China(Grant No.qn2015yx035)
文摘Radiation effects on complementary metal-oxide-semiconductor（CMOS） active pixel sensors（APS） induced by proton and γ-ray are presented. The samples are manufactured with the standards of 0.35 μm CMOS technology. Two samples have been irradiated un-biased by 23 MeV protons with fluences of 1.43 × 10^11 protons/cm^2 and 2.14 × 10^11 protons/cm-2,respectively, while another sample has been exposed un-biased to 65 krad（Si） ^60Co γ-ray. The influences of radiation on the dark current, fixed-pattern noise under illumination, quantum efficiency, and conversion gain of the samples are investigated. The dark current, which increases drastically, is obtained by the theory based on thermal generation and the trap induced upon the irradiation. Both γ-ray and proton irradiation increase the non-uniformity of the signal, but the nonuniformity induced by protons is even worse. The degradation mechanisms of CMOS APS image sensors are analyzed,especially for the interaction induced by proton displacement damage and total ion dose（TID） damage.
文摘A three-transistor active pixel sensor and its double sampling readout circuit implemented by a switch capacitor amplifier are designed. The circuit is embedded in a 64 × 64 pixel array CMOS image sensor and success-fully taped out with a Chartered 0.35μm process. The pixel pitch is 8μm × 8μm with a fill factor of 57%, the photo-sensitivity is 0.8V/（lux · s） ,and the dynamic range is 50dB. Theoretical analysis and test results indicate that as the process is scaled down, a smaller pixel pitch reduces the sensitivity. A deep junction n-well/p-substrate photodiode with a reasonable fill factor and high sensitivity are more appropriate for submicron processes.
文摘A new active digital pixel circuit for CMOS image sensor is designed consisting of four components: a photo-transducer, a preamplifier, a sample & hold (S & H) circuit and an A/D converter with an inverter. It is optimized by simulation and adjustment based on 2 μm standard CMOS process. Each circuit of the components is designed with specific parameters. The simulation results of the whole pixel circuits show that the circuit has such advantages as low distortion, low power consumption, and improvement of the output performances by using an inverter.
基金Supported by National Natural Science Foundation of China (No.60576025).
文摘A double sampling circuit to eliminating fixed pattern noise(FPN) in CMOS image sensor (CIS) is presented. Double sampling is implemented by column switch capacitor amplifier directly, and offset compensation is added to the amplifier to suppress column FPN. The amplifier is embedded in a 64×64 CIS and successfully fabricated with chartered 0.35 μm process. Theory analysis and circuit simulation indicate that FPN can be suppressed from millivolt to microvolt. Test results show that FPN is smaller than one least-significant bit of 8 bit ADC. FPN is reduced to an acceptable level with double sampling technique implemented with switch capacitor amplifier.
文摘A single CMOS image sensor based on a 0.35μm process along with its design and implementation is introduced. The architecture of an active pixel sensor is used in the chip. The fill factor of a pixel cell can reach 43%,higher than the traditional factor of 30%. Moreover, compared with the conventional method whose fixed pattern noise （FPN） is around 0.5%, a dynamic digital double sampling technique is developed, which possesses simpler circuit architecture and a better FPN suppression outcome. The CMOS image sensor chip is implemented in the 0.35μm mixed signal process of a Chartered by MPW. The experimental results show that the chip operates welt,with an FPN of about 0.17%.
基金Project supported by the National Natural Science Foundation of China(Grant No.11675259)the West Light Foundation of the Chinese Academy of Sciences(Grant Nos.2016-QNXZ-B-8 and 2016-QNXZ-B-2)
文摘A pinned photodiode complementary metal–oxide–semiconductor transistor（CMOS） active pixel sensor is exposed to ^60Co to evaluate the performance for space applications. The sample is irradiated with a dose rate of 50 rad（SiO2）/s and a total dose of 100 krad（SiO2）, and the photodiode is kept unbiased. The degradation of dark current, full well capacity,and quantum efficiency induced by the total ionizing dose damage effect are investigated. It is found that the dark current increases mainly from the shallow trench isolation（STI） surrounding the pinned photodiode. Further results suggests that the decreasing of full well capacity due to the increase in the density, is induced by the total ionizing dose（TID） effect, of the trap interface, which also leads to the degradation of quantum efficiency at shorter wavelengths.
文摘A single Complementary Metal Oxide Semiconductor (CMOS) image sensor based on 0.35μm process along with its design and implementation is introduced in this paper. The pixel ar-chitecture of Active Pixel Sensor (APS) is used in the chip,which comprises a 256×256 pixel array together with column amplifiers,scan array circuits,series interface,control logic and Analog-Digital Converter (ADC). With the use of smart layout design,fill factor of pixel cell is 43%. Moreover,a new method of Dynamic Digital Double Sample (DDDS) which removes Fixed Pattern Noise (FPN) is used. The CMOS image sensor chip is implemented based on the 0.35μm process of chartered by Multi-Project Wafer (MPW). This chip performs well as expected.
