Design and Test of a CMOS Low Noise Amplifier in Bluetooth Transceiver

A RF low noise amplifier,integrated in a single bluetooth transceiver chip and fabricated in 0.35μm digital CMOS technology,is presented.Under the consideration of ESD protection and package,design methodology is discussed from the aspects of noise optimization,impedance match,and forward gain.At 2.05GHz,the measured S 11 is -6.4dB, S 21 is 11dB with 3dB-BW of 300MHz,and NF is about 5.3dB.It indicates that comprehensive consideration of parasitics,package model,and reasonable process is necessary for RF circuit design.

一种紧凑的射频CMOS放大器LC输出匹配电路

提出了一种紧凑的射频互补金属氧化物半导体(Complementary Metal Oxide Semiconductor,CMOS)放大器LC输出匹配电路,利用放大器漏极偏置电感、输出端隔直电容与放大器输出端并联电感电容形成高阶LC谐振网络,可在占用较小芯片面积的条件下实现较传统L型匹配电路更宽频率范围的输出阻抗匹配。推导了该LC输出匹配电路元件值的计算式,并根据提出的设计方法,采用65 nm CMOS工艺设计了一款K频段放大器,其输出匹配电路尺寸仅98μm×150μm。仿真结果表明,在16.5~22.1 GHz频率范围内放大器的S 22<-10 dB,阻抗匹配带宽相比L型匹配电路增加166%。放大器实测S参数和仿真结果相符,验证了该LC匹配电路可实现紧凑的宽带阻抗匹配。

A CMOS Power Amplifier with 100% and 18% Modulation Depth for Mobile RFID Readers

Aiming at the specific protocol of RFID technology,a 915MHz CMOS transmitter front-end for OOK modulation is implemented in a 0.18μm CMOS process. The transmitter incorporates a class-E power amplifier （PA）, a modulator, and a control logic unit. The direct-conversion architecture minimizes the required on-and-off-chip components and provides a low-cost and efficient solution. A novel structure is proposed to provide the modulation depth of 100% and 18% ,respectively. The PA presents an output ldB power of 17.6dBm while maintaining a maximum PAE of 35.4%.

5Gb/s 0.25μm CMOS Limiting Amplifier

A limiting amplifier (LA) IC implemented in TSMC standard 0.25μm CMOS technology is described.Active inductor loads and direct-coupled technology are employed to increase the gain,broaden the bandwidth,reduce the power dissipation,and keep a tolerable noise performance.Under a 3.3V supply voltage,the LA core achieves a gain of 50-dB with a power consumption below 40mW.The measured input sensitivity of the amplifier is better than 5m V _ pp .It can operate at bit rates up to 7Gb/s with an rms jitter of 0.03 UI or less.The chip area is only 0.70mm×0.70mm.According to the measurement results,this IC is expected to work at the standard bit rate levels of 2.5,3.125,and 5Gb/s.

A 155Mbps 0.5μm CMOS Limiting Amplifier

This paper presents a 155Mbps limiting amplifier for STM-1 systems of SDH optical communication. It is implemented in CSMC 0.5μm CMOS technology. Under a supply voltage of 3.3V, it has a power consumption of 198mW. The core of the circuit is composed of 6 cascaded amplifiers that are in a conventional structure of differential pairs,an output buffer, and a DC offset cancellation feedback loop. The small signal gain can be adjusted from 74 to 44dB by an off-chip resistor. The chip was packaged before being tested. The experimental results indicate that the circuit has an input dynamic range of 54dB and provides a single-ended output swing of 950mV. Its output eye diagram remains satisfactory when the pseudo-random bit sequence （PRBS） input speed reaches 400Mbps.

一种基于55 nm CMOS工艺的V波段高功率宽带功率放大器

基于标准55 nm CMOS工艺设计了一款工作在V波段下的高输出功率宽带功率放大器,放大器采用交叉中和电容技术来提高功率放大器的增益和稳定性,并通过两路功率合成网络提高输出功率。通过多频点叠加技术设计级间变压器,拓展放大器带宽。仿真结果表明,在1.2 V电源电压下,放大器的3 dB带宽为14.5 GHz,静态直流功耗为184 mW,饱和输出功率为13.2 dBm,小信号增益为16.6 dB,具有高宽带、高输出功率的优点。

用于高精度模数转换器的CMOS可变增益放大器

针对工业领域数据采集系统对大摆幅模拟信号精确采样的需求,提出了一种方便与高精度模数转换器(ADC)集成的CMOS可变增益放大器(VGA)。该VGA基于反相放大器结构,在5 V单电源供电的条件下支持最大±10 V信号输入。对传递函数的设计和电路结构的优化可保证VGA高线性度的同时不降低信噪比(SNR)。电路采用TSMC 0.18μm CMOS工艺进行设计并流片,面积为0.23 mm^(2),5 V供电时功耗为1.5 mW。在输入信号1 kHz、采样率200 kS/s条件下,将VGA与16 bit逐次逼近寄存器(SAR)ADC进行联合测试,测试结果表明信噪比达到89.80 dB,总谐波失真(THD)为-102.31 dB。该VGA具有输入范围大、精度高、面积小的特点,为工业信号采集应用提供了高集成度的解决方案。

紧凑型D波段宽带CMOS低噪声放大器

基于28-nm CMOS工艺,设计了一款工作于D波段的紧凑型、宽带低噪声放大器。该放大器由四级放大器单元级联而成,每级放大器单元均采用基于中和电容技术的差分共源极结构。输入、输出和级间阻抗匹配电路均由变压器网络实现,并且每个放大器单元的中心工作频率被交错配置在120GHz和155GHz附近以实现参差调谐带宽拓展,从而在宽带内实现了平坦的增益响应。仿真和测试结果表明,在34mW直流功耗下,该放大器在中心频率140GHz处实现了19.5dB的峰值增益和28GHz(128GHz~156GHz)的3dB工作带宽,噪声系数和输入1dB压缩点分别为7.8dB~9.2dB和-19.8dBm~-16.6dBm。芯片的核心面积仅为200μm×550μm。

Design of CMOS class-E power amplifier for low power applications

A fully integrated class-E power amplifier（PA） at 2.4 GHz implemented in a 0. 18 μm 6-metal-layer mixed/RF CMOS （ complementary metal-oxide-semiconductor transistor ） technology is presented. A two-stage amplification structure is chosen for this PA. The driving stage produces a high swing switch signal by using resonation technology. The output stage is designed as a class-E topology to realize the power amplification. Under a 1.2 V power supply, the PA delivers a maximum output power of 8. 8 dBm with a power-added efficiency （PAE） of 44%. A new power control method for the class-E power amplifier is described. By changing the amplitude and duty cycle of the signal which enters the class-E switch transistor, the output power can be covered from - 3 to 8. 8 dBm through a three-bit control word. The proposed PA can be used in low power applications, such as wireless sensor networks and biotelemetry systems.

Design and simulation of Gaussian shaping amplifier made only with CMOS FET for FEE of particle detector

The objective of this paper is to design and simulate a shaping amplifier circuit for silicon strip,Si(Li),CdZnTe and CsI detectors,etc.,which can be further integrated the whole system and adopted to develop CMOS-based application,specific integrated circuit for Front End Electronics(FEE) of read-out system of nuclear physics,particle physics and astrophysics research,etc.It's why we used only CMOS transistor to develop the entire system.A Pseudo-Gaussian shaping amplifier made by fourth-order integration stage and a differentiation stage give a result same as a true CR-RC4 filter,we perform shaping time in the range,465 ns to 2.76μs with a low output resistance and the linearity almost good.

Inductorless CMOS Low Noise Amplifier for Multiband Application in 0.1–1.2 GHz

A 0.18 μm CMOS low noise amplifier(LNA) by utilizing noise-canceling technique was designed and implemented in this paper. Current-reuse and self-bias techniques were used in the first stage to achieve input matching and reduce power consumption. The core size of the proposed CMOS LNA circuit without inductor was only 128 μm 9226 μm. The measured power gain and noise figure of the proposed LNA were 20.6 and 1.9 dB,respectively. The 3-dB bandwidth covers frequency from 0.1 to 1.2 GHz. When the chip was operated at a supply voltage of 1.8 V, it consumed 25.69 mW. The high performance of the proposed LNA makes it suitable for multistandard low-cost receiver front-ends within the above frequency range.

A 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier

In this letter,we design and analyze 0.1–1.5 GHz multi-octave quadruple-stacked CMOS power amplifier(PA)in 0.18μm CMOS technology.By using two-stage quadruple-stacked topology and feedback technology,the proposed PA realizes an ultra-wideband CMOS PA in a small chip area.Wideband impedance matching is achieved with smaller chip dimension.The effects of feedback resistors on the RF performance are also discussed for this stacked-FET PA.The PA shows measured input return loss(<–10.8 dB)and output return loss(<–9.6 dB)in the entire bandwidth.A saturated output power of 22 dBm with maximum 20%power added efficiency(PAE)is also measured with the drain voltage at 5 V.The chip size is 0.44 mm^2 including all pads.

130 nm CMOS Multi-Stage Synthetic Transmission Line Based Amplifier Beyond 100 GHz

A 130 nm CMOS complementary-conducting-strip transmission line(CCS-TL)based multi-stage amplifier beyond 100 GHz was presented in this paper. Different structural parameters were investigated to achieve higher quality factor for the matching circuits. Moreover, CCS-TL based Marchand balun was implemented to achieve higher output power. The measured small signal gain was higher than 5 d B from 101 GHz to 110 GHz. DC power consumption was 67.2 mW with V_D=1.2 V, and the chip size including contact PADs was 1.12 mm×0.81 mm.

High-Speed CMOS Sample- and-Hold Amplifier

A newly designed sample-and-hold(S/H) integrated circuit based on the 1.5 micr on N-w ell CMOS technology for 8-bit high-speed analog to digital converter is descri be d. It can realize the 40-MHz sampling rate and 8-bit resolution. The good perf or mance of S/H circuit benefits from the use of a newly designed regulated cascod e operator amplifier, which has a DC gain of 140-dB, unity-gain bandwidth of 407-MHz, phase margin of 53 degree and power consumption of 90mW. It is superi or to the operator amplifier of 60\|dB, 107\|MHz, 13 degree, and 33mW respective ly, which is used in the similar S/H circuit based on the 0.8 micron technology and designed by Michio Yotsuyanagi.

A wideband CMOS variable gain low noise amplifier

In this paper, a novel structure of linear-in-dB gain control is introduced. Based on this structure, a wideband variable gain low noise amplifier （VGLNA） has been designed and implemented in 0.18μm RF CMOS technology. The measured resuhs show a good linear-in-dB gain control characteristic with 15 dB dynamic range. It can operate in the frequency range of MHz and consumes 30mW from 1.8V power supply. The minimum noise figure is 4.1 dB at the 48 - 860 maximum gain and the input P1dB is greater than - 16.5dBm.

An Enhanced Bulk-Driven Folded-Cascode Amplifier in 0.18 µm CMOS Technology

A new configuration of Bulk-Driven Folded-Cascode (BDFC) amplifier is presented in this paper. Due to this modifying, significant improvement in differential DC-Gain (more than 11 dB) is achieved in compare to the conventional structure. Settling behavior of proposed amplifier is also improved and accuracy more than 8 bit for 500 mV voltage swing is obtained. Simulation results using HSPICE Environment are included which validate the theoretical analysis. The amplifier is designed using standard 0.18 μm CMOS triple-well (level 49) process with supply voltage of 1.2 V. The correct functionality of this configuration is verified from –50℃ to 100℃.

A 28GHz Power Amplifier with Analog Predistortion Linearizer in 65nm CMOS

This paper proposes that a radio frequency power amplifier is suitable for a 5G millimeter wave.It adopts a three-stage single-ended structure at 28GHz.An analog predistortion lmearization method is used to improve the linearity of the power amplifier(PA).As a result,there is a significant improvement in power-added efficiency(PAE)and linearity is achieved.The Ka-band PA is implemented in TSMC 65nm CMOS process.At 1.2V supply voltage,the PA proposed in this paper achieves a saturated output power of 15.9dBm and a PAE of 16%.After linearization,the output power at the ldB compression point is increased by 2dBm,with efficient gain compensation performance.

基于0.18μm CMOS工艺的300GHz高响应度探测器

基于0.18μm CMOS工艺设计了一种300 GHz高响应度探测器。该探测器集成了双馈差分天线和双场效应管(FET)对称差分自混频电路。双馈差分天线较单馈天线有更高的精确度及更优的抗干扰性。差分自混频电路能有效地抑制共模信号,减小噪声输入。双场效应管后增加一级放大电路,将自混频电路输出的微弱信号进一步放大以增大响应度。天线与电路间的匹配网络实现了信号的最大功率传输。在全波电磁场仿真软件HFSS下对双馈天线进行建模与仿真优化,并与电路进行联合仿真。结果显示探测器在栅源电压为0.43 V、输入功率为-40 dBm时,最大响应度为11.25 kV/W,最小噪声等效功率为115pW/√Hz。

一种低失调CMOS轨到轨运算放大器研究

基于CMOS工艺设计了一款轨到轨运算放大器,整体电路包括偏置电路、输入级、输出级以及ESD保护电路。电路中的输入级使用了一种全新的架构,通过一对耗尽型NMOS管作为输入管,实现轨到轨输入,同时在输入级采用了共源共栅结构,能够提供较高的共模输入范围和增益;在输出级,为了得到满摆幅输出而采用了AB类输出级;同时ESD保护电路采用传统的GGMOS电路,耐压大于2 kV。经过仿真后可知,电路的输入偏置电流为150 fA,在负载为100 kΩ的情况下,输出最高和最低电压可达距电源轨和地轨的20 mV范围内,当电源电压为5 V时能获得80 dB的CMRR和120 dB的增益,相位裕度约为50°,单位增益带宽约为1.5 MHz。