This paper describes the design of a 14-bit 20 Msps analog-to-digital converter（ADC）,implemented in 0.18μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and ...This paper describes the design of a 14-bit 20 Msps analog-to-digital converter（ADC）,implemented in 0.18μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power.The proposed ADC consumes only 166 mW under 1.8 V supply.A fast background calibration is utilized to ensure the overall ADC linearity.展开更多
文摘This paper describes the design of a 14-bit 20 Msps analog-to-digital converter（ADC）,implemented in 0.18μm CMOS technology,achieving 11.2 effective number of bits at Nyquist rate.An improved SHA-less structure and op-amp sharing technique is adopted to significantly reduce the power.The proposed ADC consumes only 166 mW under 1.8 V supply.A fast background calibration is utilized to ensure the overall ADC linearity.
