通过对三值静态随机存储器(Static Random Access Memory,SRAM)单元和数据比较电路结构以及碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的研究,提出了基于CNFET的三值内容寻址存储器单元设计方案。首先利用CNFE...通过对三值静态随机存储器(Static Random Access Memory,SRAM)单元和数据比较电路结构以及碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的研究,提出了基于CNFET的三值内容寻址存储器单元设计方案。首先利用CNFET阈值可调特性和开关信号理论设计三值缓冲器,采用反馈控制连接技术实现三值SRAM存储;然后结合三值SRAM单元和三值逻辑原理设计三值内容寻址存储器单元;最后实验验证,所设计的三值内容寻址存储器单元具有正确的逻辑功能,且与三态内容寻址存储器单元相比功耗延时积(Power-Delay Product,PDP)降低约83%。展开更多
通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)多阈值特性和多值逻辑原理的研究,结合移位寄存器设计方法,提出基于CNFET的具有左移右移并入并出功能的三值脉冲型移位寄存器设计方案.该方案首先利用开关信...通过对碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)多阈值特性和多值逻辑原理的研究,结合移位寄存器设计方法,提出基于CNFET的具有左移右移并入并出功能的三值脉冲型移位寄存器设计方案.该方案首先利用开关信号理论和CNFET特性设计三值D触发器;然后设计三值T运算电路,并实现数据选择器逻辑功能;最后,在此基础上设计基于CNFET的三值脉冲型移位寄存器.经实验验证,所设计的电路输出稳定,具有正确的逻辑功能,且与CMOS低功耗移位寄存器相比,功耗延时积(Power-Delay Product)降低76.7%.展开更多
Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have c...Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.展开更多
The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally ...The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.展开更多
The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several...The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several effective approaches have been proposed based on a numerical insight into the working mechanism of T-CNFETs：tuning the doping level of source/drain leads,minimizing the quantum capacitance value via tuning the bias condition or increasing the insulator capacitance,and adopting a staircase doping strategy in the drain lead.Non-equilibrium Green＇s function based simulation results show that all these approaches can contribute to a smaller average inverse sub-threshold slope, which is quite desirable in high-frequency or low-power applications.展开更多
Carbon nanotube field effect transistor（CNFET） shows lower threshold voltage and smaller leakage current in comparison to its CMOS counterpart. In this paper, two kinds of CNFET-based rectifiers, full-wave rectifier...Carbon nanotube field effect transistor（CNFET） shows lower threshold voltage and smaller leakage current in comparison to its CMOS counterpart. In this paper, two kinds of CNFET-based rectifiers, full-wave rectifiers and voltage doubler rectifiers are presented for biomedical implantable applications. Based on the standard 32 nm CNFET model, the electrical performance of CNFET rectifiers is analyzed and compared. Simulation results show the voltage conversion efficiency（VCE） and power conversion efficiency（PCE） achieve 70.82% and 72.49% for CNFET full-wave rectifiers and 56.60% and 61.17% for CNFET voltage double rectifiers at typical 1.0 V input voltage excitation, which are higher than that of CMOS design. Moreover, considering the controllable property of CNFET threshold voltage, the effect of various design parameters on the electrical performance is investigated.It is observed that the VCE and PCE of CNFET rectifier increase with increasing CNT diameter and number of tubes. The proposed results would provide some guidelines for design and optimization of CNFET-based rectifier circuits.展开更多
通过对文字运算电路和三值存储器原理的分析,结合碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的特性,提出一种基于三值文字电路的碳纳米场效应晶体管SRAM设计方案。该方案首先利用三值文字运算真值表和开关信...通过对文字运算电路和三值存储器原理的分析,结合碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的特性,提出一种基于三值文字电路的碳纳米场效应晶体管SRAM设计方案。该方案首先利用三值文字运算真值表和开关信号理论设计文字运算电路;然后采用文字0、文字1和文字2非运算电路实现三值SRAM的功能,利用传输门控制反馈回路降低三值写操作的动态功耗;最后实验验证,所设计的电路逻辑功能正确且与传统交叉耦合SRAM相比写速度提高49.2%。展开更多
Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based tr...Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.展开更多
双极性传输特性是制约碳纳米管场效应管(carbon nanotube field effect transistors,CNFETs)性能提高的一个重要因素.为降低器件的双极性传输特性并获得较大的开关电流比,提出了一种漏端梯度掺杂策略,该策略不仅适合于类MOS碳纳米管场...双极性传输特性是制约碳纳米管场效应管(carbon nanotube field effect transistors,CNFETs)性能提高的一个重要因素.为降低器件的双极性传输特性并获得较大的开关电流比,提出了一种漏端梯度掺杂策略,该策略不仅适合于类MOS碳纳米管场效应管(C-CNFETs),同时也适合于隧穿碳纳米管场效应管(T-CNFETs).基于非平衡格林函数的数值研究结果表明,该策略不仅能有效降低器件的双极传输特性,而且能将器件开关电流比提高数个数量级.进一步研究发现,该掺杂策略在这两类碳纳米管场效应管器件结构中的应用存在诸多差异:C-CNFETs中可能发生的能级钳制将削弱器件导通状态性能,而T-CNFETs中无此现象;C-CNFETs中源、漏两端均采用梯度掺杂能进一步提高器件性能,而该策略并不适于T-CNFETs;梯度掺杂后的T-CNFETs器件性能受轻度掺杂区域宽度的影响较C-CNFETs更为显著.同时,该梯度掺杂策略会造成一定的面积开销,因此在实际应用中应合理选取器件结构、掺杂浓度、掺杂区域宽度等参数,以获得速度、功耗与面积之间的最佳折中.展开更多
Due to carrier band-to-band-tunneling （BTBT） through channel-source/drain contacts, conventional MOS- like Carbon Nanotube Field Effect Transistors （C-CNFETs） suffer from ambipolar conductance, which deteriorates ...Due to carrier band-to-band-tunneling （BTBT） through channel-source/drain contacts, conventional MOS- like Carbon Nanotube Field Effect Transistors （C-CNFETs） suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed and all kinds of source/drain contacting conditions are considered in this paper. The non-equilibrium Green＇s function （NEGF） formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold perfor- mance, even with source/drain contacts being of Schottky type. And these are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends strongly on the choice of tuning voltage value, which should be paid much attention to obtain a proper trade-off between power and speed in application.展开更多
Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low ...Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors(CNFETs).The performance is simulated in terms of three criteria including standby-power, delay(write and read) and stability(RSNM). Compared to the novel ternary SRAM cell, our results show that the average standby-power, write and read delay of the proposed cell are reduced by 78.1%, 39.6% and 58.2%, respectively. In addition, the RSNM under process variations is 2.01× and 1.95× of the conventional and novel ternary SRAM cells, respectively.展开更多
文摘通过对三值静态随机存储器(Static Random Access Memory,SRAM)单元和数据比较电路结构以及碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的研究,提出了基于CNFET的三值内容寻址存储器单元设计方案。首先利用CNFET阈值可调特性和开关信号理论设计三值缓冲器,采用反馈控制连接技术实现三值SRAM存储;然后结合三值SRAM单元和三值逻辑原理设计三值内容寻址存储器单元;最后实验验证,所设计的三值内容寻址存储器单元具有正确的逻辑功能,且与三态内容寻址存储器单元相比功耗延时积(Power-Delay Product,PDP)降低约83%。
文摘Routing resources are the major bottlenecks in improving the performance and power consumption of the current FPGAs. Recently reported researches have shown that carbon nanotube field effect transistors(CNFETs) have considerable potentials for improving the delay and power consumption of the modern FPGAs. In this paper, hybrid CNFET-CMOS architecture is presented for FPGAs and then this architecture is evaluated to be used in modern FPGAs. In addition, we have designed and parameterized the CNFET-based FPGA switches and calibrated them for being utilized in FPGAs at 45 nm, 22 nm and 16 nm technology nodes.Simulation results show that the CNFET-based FPGA switches improve the current FPGAs in terms of performance, power consumption and immunity to process and temperature variations. Simulation results and analyses also demonstrate that the performance of the FPGAs is improved about 30%, on average and the average and leakage power consumptions are reduced more than 6% and 98% respectively when the CNFET switches are used instead of MOSFET FPGA switches. Moreover, this technique leads to more than 20.31%smaller area. It is worth mentioning that the advantages of CNFET-based FPGAs are more considerable when the size of FPGAs grows and also when the technology node becomes smaller.
文摘The next generation oflogic gate devices are expected to depend upon radically new technologies mainly due to the increasing difficulties and limitations of existing CMOS technology. MOSFET like CNFETs should ideally be the best devices to work with for high-performance VLS1. This paper presents results of a comprehensive comparative study of MOSFET-like carbon nanotube field effect transistors （CNFETs） technology based logic gate library for high-speed, low-power operation than conventional bulk CMOS libraries. It focuses on comparing four promising logic families namely： complementary-CMOS （C-CMOS）, transmission gate （TG）, complementary pass logic （CPL） and Domino logic （DL） styles are presented. Based on these logic styles, the proposed library of static and dynamic NAND-NOR logic gates, XOR, multiplexer and full adder functions are implemented efficiently and carefully analyzed with a test bench to measure propagation delay and power dissipation as a function of supply voltage. This analysis provides the right choice of logic style for low-power, high-speed applications. Proposed logic gates libraries are simulated using Synopsys HSPICE based on the standard 32 nm CNFET model. The simulation results demonstrate that, it is best to use C-CMOS logic style gates that are implemented in CNFET technology which are superior in performance compared to other logic styles, because of their low average powerdelay-product （PDP）. The analysis also demonstrates how the optimum supply voltage varies with logic styles in ultra-low power systems. The robustness of the proposed logic gate library is also compared with conventional and state-art of CMOS logic gate libraries.
基金supported by the Hi-Tech Research and Development Program of China(No.2009AA01Z114)
文摘The most attractive merit of tunneling carbon nanotube field effect transistors（T-CNFETs） is the ultra-small inverse sub-threshold slope.In order to obtain as small an average sub-threshold slope as possible,several effective approaches have been proposed based on a numerical insight into the working mechanism of T-CNFETs：tuning the doping level of source/drain leads,minimizing the quantum capacitance value via tuning the bias condition or increasing the insulator capacitance,and adopting a staircase doping strategy in the drain lead.Non-equilibrium Green＇s function based simulation results show that all these approaches can contribute to a smaller average inverse sub-threshold slope, which is quite desirable in high-frequency or low-power applications.
基金Project supported by the National Natural Science Foundation of China(Nos.61131001,61404077,61571248)the Science and Technology Fund of Zhejiang Province(No.2015C31090)+2 种基金the Natural Science Foundation of Ningbo(No.2014A610147)State Key Laboratory of ASIC&System(No.2015KF006)the K.C.Wong Magna Fund in Ningbo University
文摘Carbon nanotube field effect transistor（CNFET） shows lower threshold voltage and smaller leakage current in comparison to its CMOS counterpart. In this paper, two kinds of CNFET-based rectifiers, full-wave rectifiers and voltage doubler rectifiers are presented for biomedical implantable applications. Based on the standard 32 nm CNFET model, the electrical performance of CNFET rectifiers is analyzed and compared. Simulation results show the voltage conversion efficiency（VCE） and power conversion efficiency（PCE） achieve 70.82% and 72.49% for CNFET full-wave rectifiers and 56.60% and 61.17% for CNFET voltage double rectifiers at typical 1.0 V input voltage excitation, which are higher than that of CMOS design. Moreover, considering the controllable property of CNFET threshold voltage, the effect of various design parameters on the electrical performance is investigated.It is observed that the VCE and PCE of CNFET rectifier increase with increasing CNT diameter and number of tubes. The proposed results would provide some guidelines for design and optimization of CNFET-based rectifier circuits.
文摘通过对文字运算电路和三值存储器原理的分析,结合碳纳米场效应晶体管(Carbon Nanotube Field Effect Transistor,CNFET)的特性,提出一种基于三值文字电路的碳纳米场效应晶体管SRAM设计方案。该方案首先利用三值文字运算真值表和开关信号理论设计文字运算电路;然后采用文字0、文字1和文字2非运算电路实现三值SRAM的功能,利用传输门控制反馈回路降低三值写操作的动态功耗;最后实验验证,所设计的电路逻辑功能正确且与传统交叉耦合SRAM相比写速度提高49.2%。
文摘Scaling problems and limitations of conventional silicon transistors have led the designers to exploit novel nano-technologies. One of the most promising and feasible nano-technologies is CNT(Carbon Nanotube) based transistors. In this paper, a high-speed and energy-efficient CNFET(Carbon Nanotube Field Effect Transistor) based Full Adder cell is proposed for nanotechnology. This design is simulated in various supply voltages, frequencies and load capacitors using HSPICE circuit simulator. Significant improvement is achieved in terms of speed and PDP(Power-Delay-Product) in comparison with other classical and state-of-the-art CMOS and CNFET-based designs, existing in the literature. The proposed Full Adder can also drive large load capacitance and works properly in low supply voltages.
文摘双极性传输特性是制约碳纳米管场效应管(carbon nanotube field effect transistors,CNFETs)性能提高的一个重要因素.为降低器件的双极性传输特性并获得较大的开关电流比,提出了一种漏端梯度掺杂策略,该策略不仅适合于类MOS碳纳米管场效应管(C-CNFETs),同时也适合于隧穿碳纳米管场效应管(T-CNFETs).基于非平衡格林函数的数值研究结果表明,该策略不仅能有效降低器件的双极传输特性,而且能将器件开关电流比提高数个数量级.进一步研究发现,该掺杂策略在这两类碳纳米管场效应管器件结构中的应用存在诸多差异:C-CNFETs中可能发生的能级钳制将削弱器件导通状态性能,而T-CNFETs中无此现象;C-CNFETs中源、漏两端均采用梯度掺杂能进一步提高器件性能,而该策略并不适于T-CNFETs;梯度掺杂后的T-CNFETs器件性能受轻度掺杂区域宽度的影响较C-CNFETs更为显著.同时,该梯度掺杂策略会造成一定的面积开销,因此在实际应用中应合理选取器件结构、掺杂浓度、掺杂区域宽度等参数,以获得速度、功耗与面积之间的最佳折中.
基金Project supported by the National High-Tech Research & Development Program of China(Nos.2009AA01Z124,2009AA01Z114)
文摘Due to carrier band-to-band-tunneling （BTBT） through channel-source/drain contacts, conventional MOS- like Carbon Nanotube Field Effect Transistors （C-CNFETs） suffer from ambipolar conductance, which deteriorates the device performance greatly. In order to reduce such ambipolar behavior, a novel device structure based on electrostatic doping is proposed and all kinds of source/drain contacting conditions are considered in this paper. The non-equilibrium Green＇s function （NEGF） formalism based simulation results show that, with proper choice of tuning voltage, such electrostatic doping strategy can not only reduce the ambipolar conductance but also improve the sub-threshold perfor- mance, even with source/drain contacts being of Schottky type. And these are both quite desirable in circuit design to reduce the system power and improve the frequency as well. Further study reveals that the performance of the proposed design depends strongly on the choice of tuning voltage value, which should be paid much attention to obtain a proper trade-off between power and speed in application.
基金supported by the National Natural Science Foundation of China(Nos.61474068,61234002,61404076)the S&T Plan of Zhejiang Provincial Science and Technology Department(No.2016C31078)the K.C.Wong Magna Fund in Ningbo University,China
文摘Power dissipation, speed and stability are the most important parameters for multiple-valued SRAM design. To reduce the power consumption and further improve the performance of the ternary SRAM cell, we propose a low standby-power fast ternary SRAM cell based on carbon nanotube field effect transistors(CNFETs).The performance is simulated in terms of three criteria including standby-power, delay(write and read) and stability(RSNM). Compared to the novel ternary SRAM cell, our results show that the average standby-power, write and read delay of the proposed cell are reduced by 78.1%, 39.6% and 58.2%, respectively. In addition, the RSNM under process variations is 2.01× and 1.95× of the conventional and novel ternary SRAM cells, respectively.
