期刊文献+
共找到2篇文章
< 1 >
每页显示 20 50 100
基于FPGA的嵌入式以太网通信 被引量:3
1
作者 王志东 马万太 《机电一体化》 2010年第9期64-67,83,共5页
提出了一种基于FPGA和DM9000A的嵌入式以太网通信的设计方法,阐述了硬件部分的电路组成和MicroBlaze软核处理器的一些片内外设IP核,以及简化的TCP/IP协议栈的实现方法。软件采用Standalone的运行方式,软件代码直接运行在裸CPU核上。与... 提出了一种基于FPGA和DM9000A的嵌入式以太网通信的设计方法,阐述了硬件部分的电路组成和MicroBlaze软核处理器的一些片内外设IP核,以及简化的TCP/IP协议栈的实现方法。软件采用Standalone的运行方式,软件代码直接运行在裸CPU核上。与嵌入式操作系统相比,节约了系统资源,提高了运行速度。 展开更多
关键词 FPGA 嵌入式操作系统 以太网通信 Based communication Ethernet 运行速度 TCP/IP协议栈 软核处理器 MICROBLAZE 运行方式 系统资源 实现方法 设计方法 软件代码 电路组成 cpu 硬件 外设 节约
下载PDF
wrBench:Comparing Cache Architectures and Coherency Protocols on ARMv8 Many-Core Systems
2
作者 高琬蓉 方建滨 +2 位作者 黄春 徐传福 王峥 《Journal of Computer Science & Technology》 SCIE EI CSCD 2023年第6期1323-1338,共16页
Cache performance is a critical design constraint for modern many-core systems.Since the cache often works in a"black-box"manner,it is difficult for the software to reason about the cache behavior to match t... Cache performance is a critical design constraint for modern many-core systems.Since the cache often works in a"black-box"manner,it is difficult for the software to reason about the cache behavior to match the running software to the underlying hardware.To better support code optimization,we need to understand and characterize the cache be-havior.While cache performance characterization is heavily studied on traditional x86 architectures,there is little work for understanding the cache implementations on emerging ARMv8-based many-cores.This paper presents a comprehensive study to evaluate the cache architecture design on three representative ARMv8 multi-cores,Phytium 2000+,ThunderX2,and Kunpeng 920(KP920).To this end,we develop wrBench,a micro-benchmark suite to measure the realized latency and bandwidth of caches at different memory hierarchies when performing core-to-core communication.Our evaluation pro-vides inter-core latency and bandwidth in different cache levels and coherency states for the three ARMv8 many-cores.The quantitative performance data is shown in tables.We mine the characteristics of caches and coherency protocols by analyzing the data for the three processors,Phytium 2000+,ThunderX2,and KP920.Our paper also provides discussions and guidelines for optimizing memory access on ARMv8 many-cores. 展开更多
关键词 ARMv8 many-core cache architecture microbenchmark core-to-core communication
原文传递
上一页 1 下一页 到第
使用帮助 返回顶部