A general model is made to analyze switching throughput of traffic manager in core routers.By designing a real traffic manager that uses the OC-48c interface,the whole system is analyzed and it is pointed out that at ...A general model is made to analyze switching throughput of traffic manager in core routers.By designing a real traffic manager that uses the OC-48c interface,the whole system is analyzed and it is pointed out that at least four HSSLs should be employed per CSIX interface when using Vitesse’s GigaStream switch chipset.Meanwhile,at the CSIX interface,the CFrame should be constructed ac-cording to the actual size of the last cell of each IP packet.The above principles can guarantee forwarding of IP pack-ets at line rate.A general relationship between throughput and buffering scheme of IP packets in the external memory is given,which is useful in the design of switch fabric in core routers.展开更多
基金supported by the National Natural Science Foundation of China(No.60173009 and No.60373007)the Hi-Tech Research and Development pragram of China(No.2002AA103011-1 and No.2003AA115110)China/Ireland Science and Technology Collaboration Research Foundation(CI-2003-02).Authors would like to thank Mr.Hu Chengchen and Mr.Li Jing for their discussions.
文摘A general model is made to analyze switching throughput of traffic manager in core routers.By designing a real traffic manager that uses the OC-48c interface,the whole system is analyzed and it is pointed out that at least four HSSLs should be employed per CSIX interface when using Vitesse’s GigaStream switch chipset.Meanwhile,at the CSIX interface,the CFrame should be constructed ac-cording to the actual size of the last cell of each IP packet.The above principles can guarantee forwarding of IP pack-ets at line rate.A general relationship between throughput and buffering scheme of IP packets in the external memory is given,which is useful in the design of switch fabric in core routers.
